(See Kevin's Slides).

From the machine (test beam FPGA board) we receive:

• 53/2 MHz RF clock
• coded trigger signal
• start-of-spill signal (we will request this)

We generate on-board a 160MHz master clock for the MaPSA chip. This could be derived from the RF clock (see notes below)

In response to a trigger, we start an acquisition/read-out cycle:

• Open shutter for programmable time
• Record time-stamp of each trigger while shutter is open in both 53MHz and 160MHz clock domains
• After shutter is closed, readout hits

We would record a time stamp in both the RF clock (53MHz )and MaPSA clock (160MHz) domains for the following:

• Start of spill (this could also reset the time stamps)
• Each trigger during acquisition (while shutter is open)
• Start and end of acquisition

In discussion after hanging up, we dicussed that indeed the 160MHz clock be derived from the RF clock as 53*3 = 159 MHz. We would have a stand-alone mode which would generate the clock from the local crystal as well.

Action items:

• Draft spec for detailed requirements (Yuri?). This can be a joint effort once started
• Work out details of test beam / machine interface with Lorenzo and Ryan (Eric, Dan)
• Find out what the status of the hardware is from Cornell

-- EricHazen - 2015-08-17