All Companies Capabilities

Arquimea Capabilities

Integration of sensors & actuators lab

Devices characterization lab, equipped with
  • Optical characterization instrumentation
  • Standard electronics instrumentation

Particularly important are TEST BENCH developed by the engineers themselves in order to characterize all the products designed in the laboratory.

Clean Room

clean room of 35m2 with spaces for classes ISO 6, ISO 7 and ISO 8, processes like
  • Bonding & Packaging
  • Micromachining
  • Testing and Verification.

Access through Collaborations

through INTA
  • environmental testing facilities
  • thermal vacuum chambers
  • shaking facilities, etc.

through Universidad Carlos III
  • Material Lab (SEM/TEM microscopy)
  • Electronics lab
  • Optoelectronics Lab
  • RadioFrequency Lab

through CSIC-IMS
  • 60 Mixed-Signal and MEMS experts, with background in Microelectronics and MEMS
  • Wafer Automatic Test Equipment
  • MEMS foundries ran by CSIC-IMS

Semefab Process Capabilities - Technology Platforms

Diffusion/Deposition (6")

  • High temperature Diffusions up to 1275 °C (SiC furnaces)
  • P-Type (BBr3) and N-Type (POCl3) furnace doping
  • LPCVD doped (In situ doping option) and undoped polysilicon
  • LPCVD standard and low stress Nitride process
  • LPCVD TEOS (TMP + TMB dopants) process

Diffusion, Thin Films & Implant

CMOS and Bipolar technologies fabrication on 4" wafers. PiN diode processes with low leakage characteristics and Low Noise JFET processes are also fabricated.
  • Diffusion up to 1250C (using SiC furnace tubes) with expertise on maintaining high bulk silicon lifetime during processing.
  • P type (Boron) doping processes either by Boron Discs, BBR3 or Boron Implantation.
  • N type (Phosphorous ,Arsenic and Antimony) doping processes either by furnace (phos only) or implant
  • LPCVD polysilicon for gate electrodes, resistors (to 1000 ohms/sq), poly to poly capacitors, trench fill, and sacrificial layers for MEMS. Low temperature option to ensure smooth surfaces.
  • LPCVD Nitride for LOCOS, capacitor dielectrics, MEMS membranes and Masking layers
  • PECVD (low temperature) Oxide, Oxynitride and Nitride for inter level dielectric (ILD), circuit passivation, stress controlled (tensile and compressive) for thin membrane MEMS applications, and as sacrificial layers for MEMS.

PECVD

  • Low temperature Oxide, Oxynitride and Nitride

Physical Vapour Deposition

  • Sputtering of Aluminium, Aluminium/Silicon, Aluminium/Copper alloys for IC and MEMS interconnect
  • Gold/Ti-Tungsten sputter for Bipolar/RF interconnect and wafer backmetals for eutectic die attach
  • Sichrome, Nichrome for highly stable resistors
  • Evaporation of Gold, Titanium, Nickel, Platinum, Aluminium, Tin and other pure metals for MEMS interconnect, under bump metallisation, solderable pads and wafer backmetals
  • Additional 2 sputtering systems (6 chambers) available for specific sputtering requirements
    • Two chambers are presently populated with Constantan and Vanadium
    • Two chambers have reactive sputter capable with an RF Sputter etch pre clean station

PVD-Fab3

  • Aluminium Silicon (1%), Aluminium Copper (1%) and TiW metals targets installed at present

Implant (4" & 6" capability)

  • Low and high dose implants for Boron, Phosphorous and Arsenic

Dry Isotropic Etch

  • Residue Free, High Selectivity, Isotropic Etching
  • Release and Sacrificial Etch steps for MEMS
  • Materials include:
    • Polysilicon, Amorphous Silicon, Single Crystal Silicon
    • Resist, polymers

Applications include
  • Membranes, cantilevers, channels and bridges
  • Processes include: Vapour XeF2, O2, CF4

Wafer Bonding

Advanced EVG520IS Wafer Bonder
  • Silicon to glass (Pyrex, Borofloat) Anodic Bonding
  • Eutectic thermo-compression bond

Plasma Etch (6")

  • Oxide, Nitride, Polysilicon, Silicon, Oxynitride, Aluminium and TiW etch
  • Plasma Resist removal
  • Silicon, Nitride, Polysilicon, SiCr and TiW plasma etch (SF6, SF6/O2)
  • Oxide and Oxynitride plasma etch (C2F6, CHF3)
  • Aluminium plasma etch (BCl3, Cl2, CH4, N2, CF4, O2)
  • Resist and Polyimide etch (O2, CF4)

Photo Lithography

Fab3 - 6" MOS/Bipolar:
  • 6" Projection aligner with 1.5µm resolution
  • 6" I-Line Stepper with 0.8µm resolution
  • 6" Front to back alignment system with 5µm resolution and front to back alignment accuracy of +/- 2µm

Fab1 - 4" MOS/Bipolar:
  • 4" Projection mask exposure to 2µm feature size'
  • 4" Front to back alignment system with 5µm resolution and front to back alignment accuracy of +/-2µm
  • 4" Proximity mask exposure to 5µm feature size with capability to align to features on the opposite side of the wafer (double side align) to an accuracy of +/-5µm.

Fab2 - 4" & 6" MEMS:
  • 4" & 6" projection mask exposure to 2µm feature size
  • 4" & 6" Proximity mask exposure to 5µm feature size with capability to align to features on the opposite side of the wafer (double side align) to an accuracy of +/-5µm
  • 6" I-Line Stepper with 0.8µm resolution (available March 2011)

Metrology

  • Ellipsometry for film thickness and refractive index measurement
  • CD SEM
  • Profileometry
  • Film stress measurement
  • Surfscan Particle/Defect Monitoring on blanket or Patterned wafers
  • Sheet Resistance Measurement
  • Metal Thickness/Resistivity measurement
  • C-V and lifetime measurement
  • Ellipsometry for film thickness and refractive index
  • Critical dimension measurement
  • White light interferometry
  • Thin film stress
  • Particle count
  • Four point probe (silicon resistivity)
  • Mgauge (metal thickness/resistivity)
  • SEM with EDAX Capability for elemental analysis

Wet Chemical Etch

Fabs 1, 2 & 3:
  • RCA type Pre-Diffusion cleans (4" & 6")
  • Oxide wet etch
  • Nitride wet etch
  • Aluminium, Silicon and TiW wet etches
  • Pre & Post metal wet resist strip
  • Phophorous & Boron Deglaze
  • Hydrofluoric etch (oxide)
  • Orthophosphorice etch (nitride)
  • Sulphuric Peroxide mix (resist removal and wafer clean)
  • Aluminium & Silicon etch chemical mixes
  • Solvent resist stripping

Fab2 MEMS:
  • Gold, NiCr and TiW chemical wet etches
  • Potassium Hydroxide for deep Silicon wet etch (MEMS membrane release)
  • Resist Lift Off processing (Acetone & NMP)

Deep Reactive Ion Etching (DRIE)

  • Deep silicon etch (Bosch process)
  • Through-wafer etching for membrane structures
  • Trench etching to stop on SOI
  • Double side SOI processing stopping on Buried Oxide from both sides.
  • Very high selectivity to oxide
  • Varying wall smoothness and aspect ratios
  • High Etch rates achievable depending on open areas

Spin on Coatings

* Resists, including lift off resist for metal patterning * Photo definable Polyimide for Passivation Layers * Sacrificial Polyimide for MEMS structuring. * Thick resist processing for DRIE and etching sacrificial layers.

Silex Wafer Processing Capabilities

  • Lithography
  • Plasma Etching
  • Plasma Deposition
  • Wafer Bonding
  • Back End
  • Furnace Processes
  • Wet Etching
  • Metallization
  • Metrology
  • Testing

(For more info, see http://www.silexmicrosystems.com/docs/silex_foundry_capabilities.pdf)

First Sensor Capabilities

Capabilities and core competency

  • 1200 m² ISO 5 class clean room area
  • Vertically integrated silicon wafer processing capability
  • Prototype assembly and packaging capabilities
  • Complete testing capabilities and failure analysis tools
  • Mask design
  • Wafer processing and chip design
  • Packaging
  • Electronic design for hybrid modules

Front end customization

  • Chip geometry – to suit your application
  • Responsivity – optimized for your operating wavelength
  • Rise time – to meet your bandwidth requirements
  • Capacitance – to reduce noise
  • Dark current – to improve dynamic range
  • Anti-reflective coating – to reduce optical losses
  • Filter on chip – to reduce ambient light effects

Back end customization

  • Filter on package – to reduce ambient light effects
  • Optical components – to include optical functions, scintillators, etc.
  • Light sources – include LEDs or laser dies to miniaturize your assembly
  • Packaging – to optimize cost and performance

Opto-electronic integration

  • Optimized gain-bandwidth product
  • Electronics for ionizing radiation
  • Temperature compensation
  • Read-out electronics
  • Additional optics
  • Ultra low noise high voltage source
  • A/D converter
  • Customized interface

4-Labs (or HTA) technical competencies

Silicon and related CMOS technologies

  • Nanoelectronics down to sub 45 nm
  • Low-power and low voltage SoC
  • 300 mm CMOS facilities
  • OLED-Integration on CMOS

State-of-the-art processes for

  • High-Voltage CMOS (3V – 120V operating voltage)
  • SiGe-BiCMOS
  • Non-Volatile-Memory in CMOS and High-Voltage CMOS

0.35μ and 0.18μ process nodes.

Austriamicrosystems Capabilities

Integrated Sensors

  • Hall Elements
  • Photo Diodes
  • Temperature Sensor

Sensor Interfaces

  • Magnetic
  • Optical
  • Resistive
  • Capacitive (MEMS)
  • Inductive

Signal Conversion

  • High Performance ADCs/DACs

Signal Processing

  • Digital Signal Processors with
  • Calibration Memory (OTP/EEPROM)
  • Embedded Microcontroller
(ROM/FLASH-based)
  • Safety Monitoring (IEC61508)

Actuation

  • Relay Driver
  • Full/Half Bridges
  • Gate Driver for
  • External Transistors
  • Integrated Low/High
  • Side Drivers
  • Capacitive Actuation (MEMS)

Communication Interfaces

  • SPI, SSI, UART
  • PWM, SENT
  • I2C, I2S
  • Automotive: CAN, LIN, FlexRay,
  • Ratiometric Analog Output

Power Management

  • Low Drop Regulator
(Vinput: max. 50V/120V)
  • DC/DC Converters
  • Protections
  • Reverse Polarity
  • Load Dump
  • EMC/EMV

Wafer Process Capability

Etch

Deep Si, deep oxide, thick metal etches
  • deep trench isolation
  • Si MEMS <1μm, 10-20μm deep
  • deeper etches (>100μm)
  • thick metal, deep via

Release

Multiple tools & methods

  • dielectrices, group IV (Si), polymers
  • gas or vapor methods

Encapsulation

Some call this wafer level packaging or thin film seal
  • Methods for Si MEMS and RF MEMS

Integration

  • Same wafer CMOS + MEMS

Manufacturing

  • ISO Standards
  • Development execution in a CMOS manufacturing line

Photek Facilities

  1. 4,500m2 factory space
  2. Class 100 assembly area
  3. Class 10,000 clean room
  4. Electro-mechanical vibration table
  5. Ultra-high vacuum processing equipment
  6. High speed (50 ps) laser pulsing equipment
  7. Wet and dry hydrogen stoving capability
  8. Inventor 3-D CAD software
  9. Protel Electronic Design Software
  10. Agilent 18 GHz sampling scope
  11. LeCroy 5 GHz digital scope
  12. Spectrometer
  13. Photometer
  14. Optical table and dark room facilities
  15. Environmental test chamber
  16. Phosphor screen production and inspection facilities
  17. Optical coating plant
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Topic revision: r1 - 2011-09-28 - SotirisFragkiskos
 
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