CiS capabilities

• Development of production-ready process modules for microsensors: translation of development findings in micro and nano-technology into series production based on standard technologies and technology modules;
• Provision of procedural and structural interfaces for micro and nano-technology components
• Provision of small and medium series processing especially for SMBs.
• Our focus in process development in microsensors and actuators is on the development integration of microengineering structuring, packaging technologies, system carriers/housing for micro and nano-technological components in series production-ready technological procedures. As such, processes that are connected with the actual wafer production (master wafers) soon regain their significance.

• Isotropic and anisotropic etching
• Wafer-scale packaging technologies; especially multifunctional wafer batches
• Metallic connecting structures, especially under bump metallisation, metallic interlayers, wire bond connections, bump bond connections, soldering and solder connections, etc.

Wafer Processing

Four-inch wafer production at CiS includes the usual procedures for monolithic integration of sensor and electronic functions in silicon wafers and chips. A modern equipped clean room is used for this purpose.

The standard microstructuring procedures at CiS include:

• High temperature processes (oxidation, oxygen enrichment DO, diffusion, carrier gas diffusion)
• LP-CVD (silicon nitride, high temperature oxide, poly-silicon, low temperature oxide [doped and undoped])
• PE-CVD (silicon nitride, oxynitride, silicon oxide)
• Precision cleaning processes (Carosche acid / piranha solution, RCA, HF, etc.)
• RIE and plasma etching
• WET bench (anisotropic silicon etching with and without etch stop, electrochemical isotropic silicon etching),
• Automatic enamelling and developing cluster, modified for double-sided wafer processing
• Double-sided adjustment and exposure,
• Projection lithography based on sodium-free enamel, plus lift-off masks and spray coating
• Magnetron sputters for metallisation systems (AlSi, TiN, MoSi etc.)

Modules for double-sided and three-dimensional structuring:

• Lift-off masking procedure, especially for non-CMOS-compatible materials (under-bump metallisation Ti-Ni-Au etc.)
• Spray coating
• Optimised passivation layers
• Polymer coating and structuring
• Three-dimensional modules from combinations of silicon, glass and ceramics can be implemented through wafer level connection and structuring options.

Wafer bonding

• Silicon direct bonding (SDB): high temperature and low temperature processes
• Anodic wafer bonding (AWB)
• Eutectic wafer bonding (EWB)
• Glass frit bonding
• Thermocompression bonding
• Adhesive bonding

Lift-off masking processes

Taken from in http://www.cismst.org/en/technologien/

-- SotirisFragkiskos - 02-Sep-2011