Wu is working on this. Latest word as of 5/7/08 (not tested yet):
Eric,
I have put dccv2c24.mcs to dccv4_fw.
register 0x20 was added to save BCNT offset.
It also has a modified resync algorithm and should
be able to resync HTR errors if register 0x18 is written with 0.
Shouxiang