Dummy Module Tests

Dummy module with version 1 BCCs. Photo below:

TBA

At first we followed the instructions from here (under Dummy Module Start Up Procedure). These instructions were NOT correct (specifically, the voltage on the buffer card was way too high).

Our start up procedure is as follows:

1. Flush the container holding the module with nitrogen.
2. Turn on the cooling. We set the cooling to 3 degrees Celsius.
3. Turn on the vacuum pump to ensure good thermal contact between the module and the cooling block.
4. Let the module cool; wait about 10 min.
5. Turn on the buffer card (V = 4 V, should draw current of I = 0.3 A). For us, the card draws about 0.26 A.
6. Turn on low voltage for module (V = 5 V, should draw current of I = 3 A). For us, the module draws about 3.19 A.1 Run sctdaq. To do this, type ". sct_setup.sh" into the terminal. Then type "runSCTDAQ". A new terminal should open asking for the password, once submitted root should run.
7. Run Stavelet.cpp (i.e.: ".x Stavelet.cpp").
8. In the GUI, go to window called Burst Data. Click Capture > Startup BCC V1 to capture BCC. A window will pop up saying turn off module voltage. Turn it off. Another window will pop up saying turn on module voltage. Turn it on.
9. Now we can run some tests!

May 15, 2015

Luise Poley from DESY helped us trouble shoot our system.

We ran Capture > CaptureOneHit.

First, we saw this:

This is bad. Basically, we aren't seeing the module at all. The problem turned out to be a missing line in the configuration file, as well as missing files in the folder sctdaq>var>config.

We needed the two files DUMMYmodule_60.det and DUMMYmodule_59.det. We also had to add the following lines to st_system_config.dat:

Module 0 1 1 -1 -1 -1 0 0 0 1 1 0 3 0 134 135 70 70 DUMMYmodule_59 ABCN_Test
Module 1 1 1 -1 -1 0 0 0 0 1 1 0 3 0 132 133 25 25 DUMMYmodule_60 ABCN_Test

The numbers 132-135 indicate that the data cable is connected to the HSIO at J38.

After fixing the configuration files, this was our result:

Looks different, but still aren't able to see the ASICs. This is were we discovered the issue with the voltage on the buffer card (we were running at 10 V). Once lowering to 4 V, this is what we saw:

Imagine that the bottom histogram on the left says First ABCN = 32 (I forgot to save the working OneHitTest - I'll add in the proper screen shot later; but otherwise the resulting plots looked the exact same). Basically, we can read one row of ASICs. We did try to increase the voltage slowly, to see if a higher voltage would make a difference, but it didn't help and then we concluded that doing this was probably not a good idea, so don't try it! Basically, what we see here are the IDs of the chips. The flat line at the beginning shouldn't be there. The messy looking parabolic-shaped peaks are the master chip ID. The rest of the lines are the IDs of the rest of the chips - if you count the patterns you can see that there are 10, meaning that all 10 chips in that row are responding.

For the rest of the module, our guess is that some of the wire bonds on the dummy module were damaged at some point. Will be inspecting the module to see if any wire bonds are broken.

We also tried iDelayScan (optimizes delay time in HSIO...). This is what we got:

-- LaurelleMariaVeloce - 2015-05-14