EpicSH < Main

Main Web>TWikiUsers>WeiLi>EpicSH (2024-05-20, MikhailMatveev) (raw view)
---+ *EPIC TOF Service Hybrids Project*

---++ *Project Team and Contacts*

The RDO development is a collaboration between BNL, LBNL  and Rice University:

Rice: Mike Matveev (matveev@rice.edu), Wei Li (wl33@rice.edu)

BNL: Tonko Ljubicic (tonko@bnl.gov)

JLAB: William Gu (jgu@jlab.org)
---++ *Design Requirements and General Notes*
<img alt="RDO_proto.png" src="%ATTACHURLPATH%/RDO_proto.png" width="1000" />/   </verbatim>

   * [[https://wiki.bnl.gov/EPIC/index.php/DAQ][ePIC DAQ Working Group twiki]]
   * [[https://wiki.bnl.gov/EPIC/index.php?title=Project_Information][ePIC Project Organization twiki]]
   * [[%ATTACHURL%/TOF_RDO_15-Dec-2023.pdf][TOF_RDO_15-Dec-2023.pdf]]: Block  Diagram of the RDO Prototype,  15 December 2023       </verbatim>
   * [[%ATTACHURL%/Notes_120123.pdf][Notes_120123.pdf]]: Notes, 1 December 2023    </verbatim>
   * [[%ATTACHURL%/Rad_list.pdf][Rad_list.pdf]]: Rad test results for selected commercial parts     </verbatim>
   * [[%ATTACHURL%/KCU105.pdf][KCU105.pdf]]: Xilinx KCU105 Development Board Schematic    </verbatim>
   * [[%ATTACHURL%/KCU105_MANUAL.pdf][KCU105_MANUAL.pdf]]: Xilinx KCU105 User's Guide   </verbatim>
   * [[https://u.pcloud.link/publink/show?code=kZwuIX0ZvqH6Gk3aChuPGRuw9FwEOfiEgHQ7][Most recent VHDL files ]]
   * [[https://docs.google.com/document/d/13-7ZkYIAhY5gNoGQ69XURA4lF9pMzrkC-AalILold4M/edit][Tonko's comments (with regular updates) ]]

---++ *Design Files*

---+++ *Version 1, 13 December 2023*
   * [[%ATTACHURL%/RDO.DSN][RDO.DSN]]: Orcad 9 dsn file </verbatim>
   * [[%ATTACHURL%/RDO.EDN][RDO.EDN]]: netlist EDIF 2 0 0 </verbatim>
   * [[%ATTACHURL%/RDO_CONFIG_121323.pdf][RDO_CONFIG_121323.pdf]]: FPGA configuration pdf schematic  </verbatim>
   * [[%ATTACHURL%/RDO_CLOCKS_121323.pdf][RDO_CLOCKS_121323.pdf]]: Clocks pdf schematic </verbatim>
   * [[%ATTACHURL%/RDO_OPTICS_121323.pdf][RDO_OPTICS_121323.pdf]]: Optical interfaces pdf schematic  </verbatim>
   * [[%ATTACHURL%/RDO_FMC_121323.pdf][RDO_FMC_121323.pdf]]: FMC and ETROC interfaces pdf schematic </verbatim>
   * [[%ATTACHURL%/RDO_FPGAIO1_121323.pdf][RDO_FPGAIO1_121323.pdf]]: FPGA I/O banks pdf schematic   </verbatim>
   * [[%ATTACHURL%/RDO_POWER_121323.pdf][RDO_POWER_121323.pdf]]: Power pdf schematic  </verbatim>
   * [[%ATTACHURL%/cur_meas.pdf][cur_meas.pdf]]: Current measurements; schematic example  </verbatim>

---+++ *Version 2, 16 January 2024*

   * [[%ATTACHURL%/RDO_011624.DSN][RDO_011624.DSN]]: Orcad 9 dsn file </verbatim>
   * [[%ATTACHURL%/RDO_011624.EDN][RDO_011624.EDN]]: netlist EDIF 2 0 0 </verbatim>
   * [[%ATTACHURL%/RDO_CONFIG_011624.pdf][RDO_CONFIG_011624.pdf]]: FPGA configuration pdf schematic </verbatim>
   * [[%ATTACHURL%/RDO_CLOCKS_011624.pdf][RDO_CLOCKS_011624.pdf]]: Clocks pdf schematic </verbatim>
   * [[%ATTACHURL%/RDO_OPTICS_011624.pdf][RDO_OPTICS_011624.pdf]]: Optical interfaces pdf schematic  </verbatim>
   * [[%ATTACHURL%/RDO_FMC_011624.pdf][RDO_FMC_011624.pdf]]: FMC and ETROC interfaces pdf schematic </verbatim>
   * [[%ATTACHURL%/RDO_FPGAIO1_011624.pdf][RDO_FPGAIO1_011624.pdf]]: FPGA I/O banks pdf schematic   </verbatim>
   * [[%ATTACHURL%/RDO_FPGAIO2_011624.pdf][RDO_FPGAIO2_011624.pdf]]: FPGA I/O banks pdf schematic   </verbatim>
   * [[%ATTACHURL%/RDO_POWER_011624.pdf][RDO_POWER_011624.pdf]]: Power pdf schematic  </verbatim>


---+++ *Version 3, 25 January 2024*

   * [[%ATTACHURL%/comments_012524.docx][comments_012524.docx]]: Q & A (William, Tonko) </verbatim>
   * [[%ATTACHURL%/RDO_012524.DSN][RDO_012524.DSN]]: Orcad 9 dsn file </verbatim>
   * [[%ATTACHURL%/RDO_012524.EDN][RDO_012524.EDN]]: netlist EDIF 2 0 0 </verbatim>
   * [[%ATTACHURL%/RDO_CONFIG_012524.pdf][RDO_CONFIG_012524.pdf]]: FPGA configuration pdf schematic </verbatim>
   * [[%ATTACHURL%/RDO_CLOCKS_012524.pdf][RDO_CLOCKS_012524.pdf]]: Clocks pdf schematic </verbatim>
   * [[%ATTACHURL%/RDO_OPTICS_012524.pdf][RDO_OPTICS_012524.pdf]]: Optical interfaces pdf schematic  </verbatim>
   * [[%ATTACHURL%/RDO_FMC_012524.pdf][RDO_FMC_012524.pdf]]: FMC and ETROC interfaces pdf schematic </verbatim>
   * [[%ATTACHURL%/RDO_FPGAIO1_012524.pdf][RDO_FPGAIO1_012524.pdf]]: FPGA I/O banks pdf schematic   </verbatim>
   * [[%ATTACHURL%/RDO_FPGAIO2_012524.pdf][RDO_FPGAIO2_012524.pdf]]: FPGA I/O banks pdf schematic   </verbatim>
   * [[%ATTACHURL%/RDO_POWER_012524.pdf][RDO_POWER_012524.pdf]]: Power pdf schematic  </verbatim>
   * Draft part placement  [[%ATTACHURL%/RDO_top_013024.pdf][RDO_top_013024.pdf]]:  pdf and [[%ATTACHURL%/RDO_top_013024.pptx][RDO_top_013024.pptx]]: pptx files, 30 January 2024</verbatim>

---+++ *Version 4, 1 February 2024*

   * [[%ATTACHURL%/RDO_020124.DSN][RDO_020124.DSN]]: Orcad 9 dsn file </verbatim>
   * [[%ATTACHURL%/RDO_020124.EDN][RDO_020124.EDN]]: netlist EDIF 2 0 0 </verbatim>
   * [[%ATTACHURL%/RDO_CONFIG_020124.pdf][RDO_CONFIG_020124.pdf]]: FPGA configuration pdf schematic </verbatim>
   * [[%ATTACHURL%/RDO_CLOCKS_020124.pdf][RDO_CLOCKS_020124.pdf]]: Clocks pdf schematic </verbatim>
   * [[%ATTACHURL%/RDO_OPTICS_020124.pdf][RDO_OPTICS_020124.pdf]]: Optical interfaces pdf schematic  </verbatim>
   * [[%ATTACHURL%/RDO_FMC_020124.pdf][RDO_FMC_020124.pdf]]: FMC and ETROC interfaces pdf schematic </verbatim>
   * [[%ATTACHURL%/RDO_FPGAIO1_020124.pdf][RDO_FPGAIO1_020124.pdf]]: FPGA I/O banks pdf schematic   </verbatim>
   * [[%ATTACHURL%/RDO_FPGAIO2_020124.pdf][RDO_FPGAIO2_020124.pdf]]: FPGA I/O banks pdf schematic   </verbatim>
   * [[%ATTACHURL%/RDO_POWER_020124.pdf][RDO_POWER_020124.pdf]]: Power pdf schematic  </verbatim>
   * Draft part placement  [[%ATTACHURL%/RDO_top_013024.pdf][RDO_top_013024.pdf]]:  pdf and [[%ATTACHURL%/RDO_top_013024.pptx][RDO_top_013024.pptx]]: pptx files, 30 January 2024</verbatim>

---+++ *Version 5, 13 February 2024*

   * [[%ATTACHURL%/RDO_021324.DSN][RDO_021324.DSN]]: Orcad 9 dsn file </verbatim>
   * [[%ATTACHURL%/RDO_021324.EDN][RDO_021324.EDN]]: netlist EDIF 2 0 0 </verbatim>
   * BOM  [[%ATTACHURL%/bom_021324.pdf][bom_021324.pdf]]:  pdf and [[%ATTACHURL%/bom_021324.docx][bom_021324.docx]]: docx files, 13 February 2024</verbatim>
   * PCB design requirements  [[%ATTACHURL%/RDO_req_021424.pdf][RDO_req_021424.pdf]]:  pdf and [[%ATTACHURL%/RDO_req_021424.docx][RDO_req_021424.docx]]: docx files, 14 February 2024</verbatim>
   * [[%ATTACHURL%/RDO_CONFIG_021324.pdf][RDO_CONFIG_021324.pdf]]: FPGA configuration pdf schematic </verbatim>
   * [[%ATTACHURL%/RDO_CLOCKS_021324.pdf][RDO_CLOCKS_021324.pdf]]: Clocks pdf schematic </verbatim>
   * [[%ATTACHURL%/RDO_OPTICS_021324.pdf][RDO_OPTICS_021324.pdf]]: Optical interfaces pdf schematic  </verbatim>
   * [[%ATTACHURL%/RDO_FMC_021324.pdf][RDO_FMC_021324.pdf]]: FMC interface pdf schematic </verbatim>
   * [[%ATTACHURL%/RDO_FPGAIO1_021324.pdf][RDO_FPGAIO1_021324.pdf]]: FPGA I/O banks and ETL interface pdf schematic   </verbatim>
   * [[%ATTACHURL%/RDO_FPGAIO2_021324.pdf][RDO_FPGAIO2_021324.pdf]]: FPGA I/O banks pdf schematic   </verbatim>
   * [[%ATTACHURL%/RDO_POWER_021324.pdf][RDO_POWER_021324.pdf]]: Power pdf schematic  </verbatim>
   * Draft part placement  [[%ATTACHURL%/RDO_top_020624.pdf][RDO_top_020624.pdf]]:  pdf and [[%ATTACHURL%/RDO_top_020624.pptx][RDO_top_020624.pptx]]: pptx files, 6 February 2024</verbatim>

---+++ *Version 5a, 23 February 2024 (only one clock pair on the FPGAIO2 page has been modified)*

   * [[%ATTACHURL%/RDO_022324.DSN][RDO_022324.DSN]]: Orcad 9 dsn file </verbatim>
   * [[%ATTACHURL%/RDO_022324.EDN][RDO_022324.EDN]]: netlist EDIF 2 0 0 </verbatim>
   * BOM  [[%ATTACHURL%/bom_021324.pdf][bom_021324.pdf]]:  pdf and [[%ATTACHURL%/bom_021324.docx][bom_021324.docx]]: docx files, 13 February 2024</verbatim>
   * PCB design requirements  [[%ATTACHURL%/RDO_req_021424.pdf][RDO_req_021424.pdf]]:  pdf and [[%ATTACHURL%/RDO_req_021424.docx][RDO_req_021424.docx]]: docx files, 14 February 2024</verbatim>
   * [[%ATTACHURL%/RDO_CONFIG_021324.pdf][RDO_CONFIG_021324.pdf]]: FPGA configuration pdf schematic </verbatim>
   * [[%ATTACHURL%/RDO_CLOCKS_021324.pdf][RDO_CLOCKS_021324.pdf]]: Clocks pdf schematic </verbatim>
   * [[%ATTACHURL%/RDO_OPTICS_021324.pdf][RDO_OPTICS_021324.pdf]]: Optical interfaces pdf schematic  </verbatim>
   * [[%ATTACHURL%/RDO_FMC_021324.pdf][RDO_FMC_021324.pdf]]: FMC interface pdf schematic </verbatim>
   * [[%ATTACHURL%/RDO_FPGAIO1_021324.pdf][RDO_FPGAIO1_021324.pdf]]: FPGA I/O banks and ETL interface pdf schematic   </verbatim>
   * [[%ATTACHURL%/RDO_FPGAIO2_022324.pdf][RDO_FPGAIO2_022324.pdf]]: FPGA I/O banks pdf schematic   </verbatim>
   * [[%ATTACHURL%/RDO_POWER_021324.pdf][RDO_POWER_021324.pdf]]: Power pdf schematic  </verbatim>
   * Draft part placement  [[%ATTACHURL%/place_022624.pdf][place_022624.pdf]]:  initial part placement, pdf file of  26 February 2024</verbatim>
   * Draft part placement  [[%ATTACHURL%/place_022724.pdf][place_022724.pdf]]:  initial part placement, pdf file of  27 February 2024</verbatim>

---+++ *Version 5b, 6 March 2024 (multiple changes in U5 and U7 connections)*

   * [[%ATTACHURL%/RDO_030624.PcbDoc][RDO_030624.PcbDoc]]: Altium design file, 6 March 2024 </verbatim>
   * [[%ATTACHURL%/RDO_030624.pdf][RDO_030624.pdf]]: modified pdf schematic </verbatim>
   * Initial routing  [[%ATTACHURL%/place_030624.pdf][place_030624.pdf]]:  initial routing of FMC links and clocks, pdf file of  6 March 2024</verbatim>

---+++ *Version 5c, 7 March 2024*

   * [[%ATTACHURL%/RDO_030724.PcbDoc][RDO_030724.PcbDoc]]: Altium design file, 7 March 2024 </verbatim>

---+++ *Version 5d, 12 March 2024*

   * [[%ATTACHURL%/RDO_031124.DSN][RDO_031124.DSN]]: Orcad 9 dsn file </verbatim>
   * [[%ATTACHURL%/RDO_031124.EDN][RDO_031124.EDN]]: netlist EDIF 2 0 0 </verbatim>
   * BOM  [[%ATTACHURL%/bom_031124.pdf][bom_031124.pdf]]:  pdf and [[%ATTACHURL%/bom_031124.docx][bom_031124.docx]]: docx files, 11 March 2024</verbatim>
   * [[%ATTACHURL%/RDO_CONFIG_031124.pdf][RDO_CONFIG_031124.pdf]]: FPGA configuration pdf schematic </verbatim>
   * [[%ATTACHURL%/RDO_CLOCKS_031124.pdf][RDO_CLOCKS_031124.pdf]]: Clocks pdf schematic </verbatim>
   * [[%ATTACHURL%/RDO_OPTICS_031124.pdf][RDO_OPTICS_031124.pdf]]: Optical interfaces pdf schematic  </verbatim>
   * [[%ATTACHURL%/RDO_FMC_031124.pdf][RDO_FMC_031124.pdf]]: FMC interface pdf schematic </verbatim>
   * [[%ATTACHURL%/RDO_FPGAIO1_031124.pdf][RDO_FPGAIO1_031124.pdf]]: FPGA I/O banks and ETL interface pdf schematic   </verbatim>
   * [[%ATTACHURL%/RDO_FPGAIO2_031124.pdf][RDO_FPGAIO2_031124.pdf]]: FPGA I/O banks pdf schematic   </verbatim>
   * [[%ATTACHURL%/RDO_POWER_031124.pdf][RDO_POWER_031124.pdf]]: Power pdf schematic  </verbatim>
   * [[%ATTACHURL%/RDO_schem_031124.pdf][RDO_schem_031124.pdf]]: Complete schematic in one pdf file, Pactron  </verbatim>
   * [[%ATTACHURL%/RDO_schem_031224.pdf][RDO_schem_031224.pdf]]: Complete schematic in one pdf file, Pactron  </verbatim>
   * [[%ATTACHURL%/RDO_031124.PcbDoc][RDO_031124.PcbDoc]]: Altium design file, 11 March 2024 </verbatim>
   * [[%ATTACHURL%/RDO_031224.PcbDoc][RDO_031224.PcbDoc]]: Altium design file, 12 March 2024 </verbatim>

---+++ *Version 5e, 13 March 2024*

   * BOM  [[%ATTACHURL%/BOM_031324.xlsx][BOM_031124.xlsx]]:  xlsx  file</verbatim>
   * [[%ATTACHURL%/RDO_schem_031324.pdf][RDO_schem_031324.pdf]]: Complete schematic in one pdf file, Pactron  </verbatim>
   * [[%ATTACHURL%/RDO_031324.PcbDoc][RDO_031324.PcbDoc]]: Altium design file, 13 March 2024 </verbatim>

---+++ *Version 5f, 15 March 2024*

    <img alt="RDO_3D.jpg" src="%ATTACHURLPATH%/RDO_3D.jpg" width="1000" />/  </verbatim>
    <img alt="RDOv1_rul.jpg" src="%ATTACHURLPATH%/RDOv1_rul.jpg" width="1000" />/  </verbatim>
    <img alt="RDOv1_top.jpg" src="%ATTACHURLPATH%/RDOv1_top.jpg" width="1000" />/  </verbatim>
    <img alt="RDOv1_bot.jpg" src="%ATTACHURLPATH%/RDOv1_bot.jpg" width="1000" />/  </verbatim>
    <img alt="PPRDOETL.png" src="%ATTACHURLPATH%/PPRDOETL.png" width="1000" />/  </verbatim>
    <img alt="pprdo_test.png" src="%ATTACHURLPATH%/pprdo_test.png" width="1000" />/  </verbatim>
    <img alt="HGCROC_FMC.jpg" src="%ATTACHURLPATH%/HGCROC_FMC.jpg" width="1000" />/  </verbatim>
   * BOM  [[%ATTACHURL%/BOM_031324.xlsx][BOM_031124.xlsx]]:  xlsx  file</verbatim>
   * [[%ATTACHURL%/RDO_schem_031324.pdf][RDO_schem_031324.pdf]]: Complete schematic in one pdf file, Pactron  </verbatim>
   * [[%ATTACHURL%/RDO_031524.zip][RDO_031524.zip]]: zip project file, 15 March 2024 </verbatim>
   * [[%ATTACHURL%/RDO_031524.PcbDoc][RDO_031524.PcbDoc]]: Altium design file, 15 March 2024 </verbatim>
   * [[%ATTACHURL%/RDO_032124.zip][RDO_032124.zip]]: final production zip file, 21 March 2024 </verbatim>
   * [[%ATTACHURL%/RDO_Orcad_031924.zip][RDO_Orcad_031924.zip]]: final Orcad zip file, 19 March 2024 </verbatim>
   * [[%ATTACHURL%/RDO_Gerbers_031924.zip][RDO_Gerbers_031924.zip]]: final Gerber zip files, 19 March 2024 </verbatim>
   * [[%ATTACHURL%/RDO_stack.pdf][RDO_stack.pdf]]: RDO stack-up pdf file  </verbatim>

---+++ *Debugging and Modifications, April-May 2024*

   * [[%ATTACHURL%/RDO_CLOCKS_042424.pdf][RDO_CLOCKS_042424.pdf]]: Clocks pdf schematic with modifications (R1, R2, R4, R5) </verbatim>
   * [[%ATTACHURL%/RDO_CONFIG_052024.pdf][RDO_CONFIG_052024.pdf]]: R99-R102 added to U6-14/15, U6-11/12; R19 and R21 changed from 4.7kOhm to 200 Ohm </verbatim>
    <img alt="R200.jpg" src="%ATTACHURLPATH%/R200.jpg" width="1000" />/  </verbatim>

---+++ *Prototype accounting*

   * Board #1: Rice </verbatim>
   * Board #2: Zagreb (Tonko) </verbatim>
   * Board #3: Rice </verbatim>
   * Board #4: Rice </verbatim>
   * Board #5: CEBAF (William) </verbatim>
   * Board #6: Rice </verbatim>

---+++ *Discussion*

1.     [[%ATTACHURL%/FPGA_banks.pdf][FPGA_banks.pdf]]: FPGA  banks assignment (Tonko, 3 January 2024) </verbatim>
 
2.     [[%ATTACHURL%/RDO_clocks.pdf][RDO_clocks.pdf]]: FPGA  clock assignment (William, 3 January 2024) </verbatim>

3.     [[%ATTACHURL%/notes_010424.pdf][notes_010424.pdf]]: Meeting Notes (Tonko, 4 January 2024) </verbatim>

4.    [[%ATTACHURL%/RDOclockPinouts.pdf][RDOclockPinouts.pdf]]: Schematic modifications (William, 3 January 2024) </verbatim>

5.   [[%ATTACHURL%/MONITOR.pdf][MONITOR.pdf]]: Current/Voltage measurements (Mike, 3 January 2024) </verbatim>

6.  [[%ATTACHURL%/clocks_011124.pdf][clocks_011124.pdf]]: Updated clock diagram (Tonko, 11 January 2024) </verbatim>

7. [[%ATTACHURL%/FMCV0.pdf][FMCV0.pdf]]: Schematic diagram of the HRPPD FMC board (Tonko, 11 January 2024) </verbatim>

8.  [[%ATTACHURL%/ETROC2_signals.pdf][ETROC2_signals.pdf]]: ETROC2 interface signals (Mike, 11 January 2024)  </verbatim>

9.  [[%ATTACHURL%/top.vhd][top.vhd]]: top.vhd file for the FPGA (Tonko, 15 January 2024) </verbatim>

10. [[%ATTACHURL%/constraints.xdc][constraints.xdc]] constraints.xdc file for the FPGA (Tonko, 15 January 2024) </verbatim>

11. [[%ATTACHURL%/DC_DC_table.pdf][DC_DC_table.pdf]] Comparison of bPOL12V, bPOL48V and LTC7890 converters (Tim, 16 January 2024) </verbatim>

12. [[%ATTACHURL%/William_012224.pdf][William_012224.pdf]] William's comments on schematic ver.2 </verbatim>

13.  [[%ATTACHURL%/Tonko_012324.pdf][Tonko_012324.pdf]] Tonko's comments on schematic ver.2 </verbatim>

14.  [[%ATTACHURL%/tonko_012924.pdf][tonko_012924.pdf]] Tonko's comments on schematic ver.3, 01/29/2024 </verbatim>

15.  [[%ATTACHURL%/tonko_013024.pdf][tonko_013024.pdf]] Tonko's comments on schematic ver.4, 01/30/2024 </verbatim>

16.  [[%ATTACHURL%/comments_020624.pdf][comments_020624.pdf]] Tonko's comments on schematic ver.4, 02/06/2024 </verbatim>

---++ *Interfaces*

---+++ *ETL Module Board (top 3 pictures) and Readout Board v.2. (bottom 2 pictures)*

<img alt="ETL_module.png" src="%ATTACHURLPATH%/ETL_module.png" width="1000" />/  </verbatim>
<img alt="MBv0b_top.png" src="%ATTACHURLPATH%/MBv0b_top.png" width="1000" />/  </verbatim>
<img alt="MBv0b_bot.png" src="%ATTACHURLPATH%/MBv0b_bot.png" width="1000" />/  </verbatim>
<img alt="PBv2_top.jpg" src="%ATTACHURLPATH%/RBv2_top.jpg" width="1000" />/  </verbatim>
<img alt="PBv2_bot.jpg" src="%ATTACHURLPATH%/RBv2_bot.jpg" width="1000" />/  </verbatim>


   * [[CMS.ModulePCB][ETL Module PCB twiki]]
   * [[%ATTACHURL%/Module_V0b.pdf][Module_V0b.pdf]]: Module Board v.0b schematic diagram </verbatim>
   * [[%ATTACHURL%/ETROC2_Reference_Manual_v0.44.pdf][ETROC2_Reference_Manual_v0.44.pdf]]: ETROC2 Reference Manual ver.0.44, 24 January 2024 </verbatim>
   * [[%ATTACHURL%/Bill_of_Materials-ETROC2.xlsx][Bill_of_Materials-ETROC2.xlsx]]: Module Board BOM  </verbatim>



---+++ *Optical*
   * [[%ATTACHURL%/SFP_spec.PDF][SFP_spec.PDF]]: SFP specification </verbatim>
   * [[%ATTACHURL%/sfp.png][sfp.png]]: Typical SFP connection diagram </verbatim>
   * [[%ATTACHURL%/AFBR710.pdf][AFBR710.pdf]]: AFBR-710 SFP+ optical transceiver  </verbatim>
   * [[%ATTACHURL%/VTRXP.pdf][VTRXP.pdf]]: VTRX+ Application Note  </verbatim>
   * [[%ATTACHURL%/DF40.pdf][DF40.pdf]]:  Hirose DF40C-2.0-40DS-0.4V connector for the VTRX+ optical transceiver </verbatim>

---+++ *FMC Mezzanine*
   * [[%ATTACHURL%/HRPPD-FMCV0_Schematic.pdf][HRPPD-FMCV0_schematic.pdf]]: Example of FMC card from HRPPD  </verbatim>
   * [[%ATTACHURL%/134486.pdf][134486.pdf]]: FMC HPC Connector ASP-134486-01 </verbatim>
   * [[https://fmchub.github.io/appendix/VITA57_FMC_HPC_LPC_SIGNALS_AND_PINOUT.html][VITA 57 FPGA Mezzanine card]]

---+++ *USB*
   * [[%ATTACHURL%/USB_example.png][USB_example.png]]: Example of the USB interface </verbatim>


---++ *Datasheets, Manuals and User Guides*

---+++ *FPGA Resources*

   * [[%ATTACHURL%/ug570-ultrascale-configuration.pdf][ug570-ultrascale-configuration.pdf]]: Xilinx/AMD UltraScale Architecture Configuration User Guide UG570 </verbatim>
   * [[%ATTACHURL%/ug571-ultrascale-selectio.pdf][ug571-ultrascale-selectio.pdf]]: Xilinx/AMD UltraScale Architecture SelectIO Resources User Guide UG571 </verbatim>
   * [[%ATTACHURL%/ug572-ultrascale-clocking.pdf][ug572-ultrascale-clocking.pdf]]: Xilinx/AMD UltraScale Architecture Clocking Resources User Guide UG572</verbatim>
   * [[%ATTACHURL%/ug575-ultrascale-pkg-pinout.pdf][ug575-ultrascale-pkg-pinout.pdf]]: Xilinx/AMD UltraScale and UltraScale + FPGAs Packaging and Pinouts Product Specification UG575 </verbatim>
   * [[%ATTACHURL%/UG575_2023.pdf][UG575_2023.pdf]]: Xilinx/AMD UltraScale and UltraScale + FPGAs Packaging and Pinouts Product Specification UG575 (ver 2023) </verbatim>
   * [[%ATTACHURL%/UG576_2021.pdf][UG576_2021.pdf]]: Xilinx/AMD UltraScale Architecture GTH Transceivers User Guide UG576, ver.1.7, 2021 </verbatim>
   * [[%ATTACHURL%/ug580-ultrascale-sysmon.pdf][ug580-ultrascale-sysmon.pdf]]: Xilinx/AMD UltraScale Architecture System Monitor User Guide UG580</verbatim>
   * [[%ATTACHURL%/ug583-ultrascale-pcb-design.pdf][ug583-ultrascale-pcb-design.pdf]]: Xilinx/AMD UltraScale Architecture PCB Design User Guide UG583 </verbatim>
   * [[%ATTACHURL%/ds931-artix-ultrascale-plus.pdf][ds931-artix-ultrascale-plus.pdf]]: Xilinx/AMD Artix UltraScale + FPGA Data Sheet: DC and AC Switching Characteristics DS931 </verbatim>
   * [[%ATTACHURL%/xcaup15.pdf][xcaup15.pdf]]: XCAU15P-2SBVB484 pinout </verbatim>
   * [[%ATTACHURL%/xcau484.PNG][xcau484.PNG]]: XCAU15P-2SBVB484 MGT/banks  top-view perspective of the package pinout</verbatim>
   * [[%ATTACHURL%/SBVB484.pdf][SBVB484.pdf]]: SBVB484 package dimensions</verbatim>

---+++ *Other Active Parts*

   * [[%ATTACHURL%/Si5338.pdf][Si5338.pdf]]: Si5338 Programmable Clock Generator Datasheet </verbatim>
   * [[%ATTACHURL%/SI5338_RM.pdf][SI5338_RM.pdf]]: Si5338 Reference Manual </verbatim>
   * [[%ATTACHURL%/AN360.pdf][AN360.pdf]]: Crystal Selection Guide for Si5338 </verbatim>
   * [[%ATTACHURL%/fa238.pdf][fa238.pdf]]: EPSON FA238 crystal Datasheet </verbatim>
   * [[%ATTACHURL%/SI5344.pdf][SI5344.pdf]]: Si5345 Datasheet </verbatim>
   * [[%ATTACHURL%/Si5345_RM.pdf][Si5345_RM.pdf]]: Si5345 Reference Manual </verbatim>
   * [[%ATTACHURL%/SI53302.pdf][SI53302.pdf]]: Si5330x Fanout Buffers Datasheet </verbatim>
   * [[%ATTACHURL%/MIC69502.pdf][MIC69502.pdf]]: Micrel MIC69502WR LDO Datasheet </verbatim>
   * [[%ATTACHURL%/ADCLK944.pdf][ADCLK944.pdf]]: ADCLK944 clock fanout buffer datasheet </verbatim>
   * [[%ATTACHURL%/MT25QU256.pdf][MT25QU256.pdf]]:Micron MT25QU256 SPI Flash Memory Datasheet </verbatim>
   * [[%ATTACHURL%/txb0104.pdf][txb0104.pdf]]: TI TXB0104 4-channel level converter Datasheet </verbatim>
   * [[%ATTACHURL%/max4372.pdf][max4372.pdf]]: MAX4372 current sense amplifier Datasheet  </verbatim>
   * [[%ATTACHURL%/cp2102n.pdf][cp2102n.pdf]]: USB Controller CP2102N Datasheet  </verbatim>
   * [[%ATTACHURL%/sn65lvep11.pdf][sn65lvep11.pdf]]: SN65LVEP11 Datasheet  </verbatim>
   * [[%ATTACHURL%/sn74lvc2t45.pdf][sn74lvc2t45.pdf]]: SN74LVC2T45 Voltage Level Converter Datasheet  </verbatim>
   * [[%ATTACHURL%/txs0102.pdf][txs0102.pdf]]: TXS0102 Voltage Level Converter for I2C Datasheet  </verbatim>
   * [[%ATTACHURL%/bPOL12V_V6.pdf][bPOL12V_V6.pdf]]: bPOL12V Regulator Datasheet  </verbatim>
   * [[%ATTACHURL%/KC2016.pdf][KC2016.pdf]]: KC2016 Clock Oscillator Datasheet  </verbatim>
   * [[%ATTACHURL%/LDL112.pdf][LDL112.pdf]]: ST LDL112 LDO converter datasheet  </verbatim>
   * [[%ATTACHURL%/lp3882.pdf][lp3882.pdf]]: TI LP3882 LDO converter datasheet  </verbatim>

---+++ *Other Passive Parts*
   * [[%ATTACHURL%/u77.pdf][u77.pdf]]:  Amphenol U77-A1118-200T protective cage for SFP+ transceiver </verbatim>
   * [[%ATTACHURL%/qse.pdf][qse.pdf]]: Samtec QSE-020-02-L-D-A connector </verbatim>
   * [[%ATTACHURL%/LF154.pdf][LF154.pdf]]: Littelfuse 154 Series </verbatim>
   * [[%ATTACHURL%/PJ063.pdf][PJ063.pdf]]: Power Jack PJ063  </verbatim>
   * [[%ATTACHURL%/3180400.pdf][3180400.pdf]]: Yageo 32207638 1kOhm temperature sensor  </verbatim>
   * [[%ATTACHURL%/UX76.pdf][UX76.pdf]]:  Amphenol UX76-A20-3000T 20-pin connector for SFP+ transceivers </verbatim>
   * [[%ATTACHURL%/LX0603.pdf][LX0603.pdf]]: Lumex SML-LX0603GW-TR green LED  </verbatim>
   * [[%ATTACHURL%/ihlp2020bz11.pdf][ihlp2020bz11.pdf]]: Vishay Dale IHLP2020BZER4R7M11 4.7UH inductor  </verbatim>
   * [[%ATTACHURL%/SMA.pdf][SMA.pdf]]: Rosenberger 32K10K-400L5 SMA connector  </verbatim>
   * [[%ATTACHURL%/LEMO.pdf][LEMO.pdf]]:  LEMO EPL.00.250.NTN connector  </verbatim>
   * [[%ATTACHURL%/ERJ.pdf][ERJ.pdf]]: Panasonic ERJ-B2CFR02V current sensing resistor  </verbatim>
   * [[%ATTACHURL%/690.pdf][690.pdf]]:  EDAC 690-005-299-043 USB 2.0 MINI B receptacle </verbatim>
   * [[%ATTACHURL%/B3S.pdf][B3S.pdf]]:  Omron B3S-1000 push button </verbatim>
   * [[%ATTACHURL%/134486-02.pdf][134486-02.pdf]]: Samtec ASP-134486-02 400-pin connector array   </verbatim>

---+++ *Firmware*

   * [[https://u.pcloud.link/publink/show?code=kZwuIX0ZvqH6Gk3aChuPGRuw9FwEOfiEgHQ7][Repository (Tonko)]]

   * ppRDO Firmware version 05/08/2024 (Tonko)  [[%ATTACHURL%/pprdo_download_0x42B12160.bit][pprdo_download_0x42B12160.bit]]: bit file for XCAU15P FPGA </verbatim>
   * Simple project (blinking LED)  [[%ATTACHURL%/RDO2.bit][RDO2.bit]]:  .bit file for XCAU15P FPGA and [[%ATTACHURL%/RDO2.mcs][RDO2.mcs]]: .mcs file for mt25qu256_spi_x1_x2_b4 PROM (including DIVAB=SFOUT0=SFOUT1=0 for Si53302)</verbatim>

---+++ *Presentations*
   * [[https://indico.bnl.gov/event/20473/sessions/6737/#20240109][January 2024 EPIC Collaboration Meeting ]]
   * [[%ATTACHURL%/ePICColl_SHs_01092024.pdf][ePICColl_SHs_01092024.pdf]]:  Protection diods  </verbatim>


---++ Tonko

This is the [[https://docs.google.com/document/d/105TS7gOHlNSSksMRZgHaBllftek3NvumUw7EOrVkEkU/edit][parts list.]] [external link test]

Downloaded attachment. Artix SBVB484 pin file [[%ATTACHURL%/xcau15psbvb484pkg.txt][here.]] [local attachment link test]
Attachments
Topic attachments
I	Attachment	History	Action	Size	Date	Who	Comment
txt	xcau15psbvb484pkg.txt	r1	manage	50.3 K	2023-12-05 - 12:52	AnteLjubicic	XCAU15P SBVB484 pin file
Topic revision: r94 - 2024-05-20 - MikhailMatveev
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