FNAL Prototype Pattern Recognition Mezzanine Card(protoPRM) for Pulsar2b

Device Number:

Inspector:

Anti-Static

• [ ] Before touching any boards/devices, using an anti-static wrist strap to keep your partner and yourself grounded;
• [ ] When moving any boards/devices, using anti-static bags or boxes;

Top and back view

Visual Test

• [ ] Before installing heat sink, checking the type of FPGA: UltraScale Kintex FPGA XCKU040 FFVA1156 -2E or XCKU060
• [ ] Make sure all the components are soldered properly, and in correct orientation:
  • Soldering quality;
  • Orientation of IC's: a small tick and module name is around the IC. Below is an example:
  • 
  • polarity of capacitors:13x 330uF Tantalum Capacitors
  • 
  • The two fuses (2A or 4A) are installed: left bottom corner of the back side
  • 
• [ ] Measure the resistance value between each power supplies TP (Test Point) to GND TP with a multimeter. Make sure there is no shortcut between power supplies and GND;
  • 

Power Rail	Reference Value (ohm)	Measured Value (ohm)
P0	36K(need a long time to be stable)
P1	480
P2	4.5
P3	170
P4	330
P5	310
P6	62
P7	300K

• [ ] Measure the resistors' value. ~10% difference between the reference value and measured value is acceptable.
  • 

Resistor	Value in Schematics (ohm)	Reference Value (ohm)	Measured Value (ohm)
R4	30.0K	21K
R8	10.0K	8.9K
R12	34.8K	22.8K
R16	13.3K	11.4K
R21	20.0K	16.0K

Standalone Voltage Test

Dual Output Power Supply

For standalone test, two voltages are needed: 12V and 3.3V. Below is the schematic, and pin assignment for the standalone power plug/socket. (When standalone testing, could increasing 3.3V to 3.35V)

When turning on the power, the initial currents of the 12V and 3.3V output are ~0.4A.

Board Status LED Indicators

These green colored LEDs are located on the top middle of the backside.

Test Points for All Power Planes

Voltage Polarity for Tantalum Capacitors

FPGA Firmware Test

Reminder:

1) When developing the firmware, please define the "RSETN" pin as a input port. If not, the "RSETN" pin will be in "floating" status, which could pull down the "RESET" signal (voltage of R24), and keep the whole PRM board in "reset" status;

2)...

LED Blinking Test

There are 8(8) LEDs directly controled by the master(slave) FPGA. LEDBlinker firmware is the most basic firmware, which is like the "Hello World" codes in C/C++ language. If all these LEDs are blinking as expected, the most part of our PCB design is right.

The default system clock for the master and slave FPGAs are 100MHz. The fastest LED blinking frequence is 1.5Hz.

Blinking Firmwares for XCKU040: LEDBlinker_master.bit, LEDBlinker_slave.bit

Blinking Firmwares for XCKU060: XCKU60_M_LEDBlinker.bit, XCKU60_S_LEDBlinker.bit

If you want to program the SPI Flash memory with this blinking firmware, you need "bin" file:

Bin files for XCKU040: LEDBlinker_master.bin , LEDBlinker_slave.bin;

Bin files for XCKU060: XCKU60_M_LEDBlinker.bin, XCKU60_S_LEDBlinker.bin

simple guide is here: Program_SPI_memory.pdf, Program_SPI_memory.pptx

xilinx ducoment is here: XAPP1233

After you programmed the SPI memory, when next time you turn on the mezzanine card, the firmware will be automatically loaded to the FPGA, and the LEDs start to blinking.

SPI memory type is: n25q256-3.3v-spi-x1_x2_x4

XCKU60 FPGA IBERT Test for GTH Lines

Firmwares are produced by Vivado 2015.4.2

Local GTH between Master FPGA and Slave FPGA

	6.25	8.0	12.5	16.375
Master FPGA	XCKU60_LGTH_M_6p25.bit	XCKU60_LGTH_M_8p0.bit	XCKU60_LGTH_M_12p5.bit	XCKU60_LGTH_M_16p375.bit
Slave FPGA	XCKU60_LGTH_S_6p25.bit	XCKU60_LGTH_S_8p0.bit	XCKU60_LGTH_S_12p5.bit	XCKU60_LGTH_S_16p375.bit
Power Consumption
Bit Error Rate
Eye Open Area

Setup scripts: KU060_vivado_Mezz2_localbus_setup.tcl

Eye-Diagram Drawing scripts: KU060_vivado_Mezz2_localbus_scan.tcl

QSFP+ GTH between Master FPGA and Slave FPGA

	6.25	10.3125	14.0
Master FPGA	XCKU60_QSFP_M_6p25.bit	XCKU60_QSFP_M_10p3125.bit	XCKU60_QSFP_M_14p0.bit
Slave FPGA	XCKU60_QSFP_S_6p25.bit	XCKU60_QSFP_S_10p3125.bit	XCKU60_QSFP_S_14p0.bit
Power Consumption
Bit Error Rate
Eye Open Area

Setup scripts: KU060_vivado_Mezz2_QSFP_setup.tcl

Eye-Diagram Drawing scripts: KU060_vivado_Mezz2_QSFP_scan.tcl

FMC GTH between PRM Master FPGA and Pulsar2b main FPGA

(This firmware will active all the GTHs of the PRM master FPGA): XCKU60_All_M_10_and_16p3.bit

XCKU40 FPGA IBERT Test for GTH Lines

(Please use vivado 2015.2)

PLL chosen for different Speed: QPLL0 9.8–16.3 GHz; QPLL1 8.0–13.0 GHz; CPLL <8.0 GHz

Local GTH Bus between Master FPGA and Slave FPGA

start from 6Gb/s to 16.25Gb/s; LGTH3 are special; Default reference CLK is 125MHz;

	6.25Gb/s	8.0Gb/s	10.0Gb/s	12.5Gb/s	15.625Gb/s
Master FPGA	Local_Master_6p25Gbps.bit	Local_Master_8Gbps.bit	Local_Master_10Gbps.bit	Local_Master_12p5Gbps.bit	Local_Master_15p625Gbps.bit
Slave FPGA	Local_Slave_6p25Gbps.bit	Local_Slave_8Gbps.bit	Local_Slave_10Gbps.bit	Local_Slave_12p5Gbps.bit	Local_Slave_15p625Gbps.bit

TCL script for fast setup and measure Eye-Diagrams in vivado: vivado_Mezz2_localbus_setup.tcl vivado_Mezz2_localbus_scan.tcl

QSFP+ to QSFP+ by AOC

Master FPGA 228 Quad and Slave FPGA 226 Quad are used for QSFP+ connection. The default reference clk is 156.25MHz.

	6.25Gb/s	10.3125Gb/s	14.0Gb/s
Master FPGA	QSFP_Master_6p25Gbps.bit	QSFP_Master_10p3125Gbps.bit
Slave FPGA	QSFP_Slave_6p25Gbps.bit	QSFP_Slave_10p3125Gbps.bit

TCL script for fast setup and measure Eye-Diagrams in vivado: vivado_Mezz2_QSFP_setup.tcl vivado_Mezz2_QSFP_scan.tcl

FMC GTH lines between Pulsar2b and Master FPGA

Default reference CLK is 66.66MHz.

	8.0Gb/s	10.0Gb/s
Master FPGA	FMC_Master_8Gbps.bit	FMC_Master_10Gbps.bit

(These firmwares are not suggested to be used, because the reset pin is not defined)

There is a 125MHz refclk for local GTH bus could also be used by the FMC GTH:

	6.25Gb/s	8.0Gb/s	10.0Gb/s
Master FPGA	FMC_Master_6p25Gbps_ref125.bit	FMC_Master_8Gbps_ref125.bit	FMC_Master_10Gbps_ref125.bit
Pulsar2b	bit file	bit file	bit file

TCL script for fast setup and measure Eye-Diagrams in vivado: vivado_Mezz2_FMC_setup.tcl vivado_Mezz2_FMC_scan.tcl

Run QSFP+, LOC, and FMC GTHs at Same Time

QSFP+ and FMC GTHs is driving at 10.0 Gb/s with refclk=125MHz; LOC GTHs is driving at 15.625Gb/s with refclk=125MHz;

Be careful about the FPGA Temperature.

Master FPGA: MasterFPGA_AllGTH.bit

Slave FPGA: SlaveFPGA_AllGTH.bit

LVDS Bus

LVDS Bus is several 1Gb/s I/O lines. 1.8V

Local LVDS between Master and Slave FPGA

24 pairs LVDS

Master and Slave FPGA (KU040) at 200MHz: KU040_M_LVDS_BERT.bit, KU040_S_LVDS_BERT.bit

Master and Slave FPGA (KU060) at 200MHz: KU060_M_LVDS_BERT.bit, KU060_S_LVDS_BERT.bit

debug file: debug_nets.ltx

FMC LVDS between Pulsar2b and Master FPGA

22 pairs each FMC connector

Pulsar2b FMC1-4: PL2b_FMC1_LVDS_BERT.bit, PL2b_FMC2_LVDS_BERT.bit, PL2b_FMC3_LVDS_BERT.bit, PL2b_FMC4_LVDS_BERT.bit;

PRM with KU040 FPGA: PRM40_FMC0_LVDS_BERT.bit, PRM40_FMC1_LVDS_BERT.bit

PRM with KU060 FPGA: PRM60_FMC0_LVDS_BERT.bit, PRM60_FMC1_LVDS_BERT.bit

Debug file: FMC_LVDS_debug_nets.ltx

I2C Interface

The Master FPGA could control the clock generator, temperature sensor, QSFP+ connectors, and voltage regulators through I2C.

Clock Generator

The default clock frequencies provied by the clock generator are:

CLOCK	F(MHz)	AC coupling Capacitors
Master FPGA QSFP	156.25	C56,60
Slave FPGA QSFP	156.25	C63,64
Master FPGA Local Bus	125	C65,66
Slave FPGA Local Bus	125	C67,68
Master FPGA FMC	66.66	C67,68
Master FPGA SYSCLK	100	C74,75
Slave FPGA SYSCLK	100	C71,72

The simplest way to measure the frequency is by checking the AC coupling capacitors with oscilloscope, but be careful. By this way, you don't need programming the FPGA's.

There are 2 firmwares, LEDBlinker_clock_forward_master.bit and LEDBlinker_clock_forward_slave.bit, that could forward the sysclk, QSFP+, LOC, and FMC refCLK to testpoint. The master FPGA's clocks are sent to P11, and slave FPGA's are sent to P12.

TP[0] is sysclk, TP[1] is QSFP+ clk, TP[2] is local bus clk, and TP[3] is fmc clk. (There is no fmc clk in slave FPGA)

Could use I2C interface to change the clock generator output frequency: top_changeY0Y1from156p25to125.bit and top_changeY2Y3from125to250.bit

Here is a simple I2C master VHDL code: https://www.eewiki.net/display/LOGIC/I2C+Master+(VHDL).

SRAM

Static RAM is a low latence memory device.

VIPRAM

Next generation VIPRAM Chip

-- ZijunXu - 2015-05-26