Input Handler Cookbook

EDA Tools needed to recompile project

All the software is installed on the PCLIP6 and mapped to PATH env. variable.

1. Xilinx ISE, 9.2sp4, IP-update2
2. Cygwin ( Xilinx EDK), Xilinx EDK 9.2sp2
3. Synplify Pro, SynPro 8.9
4. Eclipse editor, which by default starts in projects directory.
5. If Eclipse is being used then the veditor is recommended for VHDL/Verilog syntax highlighting.
6. QuestaSim for simulation, PCLIP6 has 6.3d installed.

Installation versions of the Xilinx ISE, Xilinx EDK, Chipscope, and Synplify PRO can be found on CAE PROGS repository. The QuestaSim simulator can be found on the PCLIP6, in the e:/Istanlls directory.

Project repository

The IH's firmware is being stored in the CERN CVS repository. All files can be downloaded from this place. To download the last release (10.07.2008 version):

1. Go to the http://isscvs.cern.ch/cgi-bin/cvsweb.cgi/dcc_ih/?cvsroot=cmsdcc;only_with_tag=LAST_UPLOADED_BY_MH This will select the latest ( 10.07.2008) release.
2. Click on the "Download tarball" ( !!! It takes few seconds to prepare tarball).

CVS client configuration:

1. Connection type: extssh
2. User: your account name
3. CVS server: isscvs.cern.ch
4. Port: default
5. CVS CMS DCC Repository path: /local/reps/cmsdcc
6. Module: dcc_ih
7. Tag: LAST_UPLOADED_BY_MH

Project structure

To simplify project management all the files are grouped by functionality. The IH project's root directory contains 4 subdirectories which are listed and described bellow:

• imp - all files generated during the ISE's Mapping, Place & Route phases.
• sim - all testbenches, simulation scripts and waveform description files.
• src -project source files - Verilog, SystemVerilog and Xilinx XCO files. The XCO files are needed by Xilinx's Coregen tool to recreate module's description netlists.
• syn - contains Syplify PRO project file and synthesis constraint file.

The data flow looks as follows: the source files stored in src directory are being synthesized by Synplify PRO tool, the synthesis result ( EDIF file) is placed in syn/dcc_ih_6_sr_chn (8 channel version) or syn/dcc_ih_6_sr_chn ( 6 channel version) directories.

How to compile design

The project compilation process is being managed by makefile tool. It automatically checks which parts of the project ( synthesis, mapping, place&route, or bitfile generation) need to be redone. This tool is accessible under windows from Cygwin UNIX like shell.

After starting Cygwin, the project can be accessed by moving to f:/Projects/FPGA/LIP/ih_v3 directory.

Test System

Then you have to execute following commands ( in order):

1. make clean - to clean working directories
2. make regen_cores - to regenerate modules created with ISE COREGEN tool

Now, when all libraries are prepared, the synthesis shall be performed:

1. make syn_6 - to synthesize IH 6 channel version
2. make syn_8 - to synthesize IH 8 channel version

When synthesis is done, the Place and Route will generate the BIT and MSK files:

1. make par_6 - to map, place&route 6 channel version
2. make par_8 - to map, place&route 8 channel version

Viewing synthesis results with Synplify PRO GUI

The results of the IH synthesis can be viewed by using the Synplify's PRO RTL viewer.

1. Start the Synplify PRO GUI
2. Open the IH project top.prj located in the syn/ directory of the IH repository
3. If not already done, perform the synthesis by clicking RUN button in main pane.
4. View the result by clicking

How to create PROM files from BIT & MSK files

This part has not been automated yet. You need to start iMPACT GUI to generate PROM files. The procedure is as follow:

1. Generate BIT&MSK files with procedure described above.
2. The MSK and BIT files are placed in imp/dcc_ih_6_sr_chn or imp/dcc_ih_6_sr_chn
3. Start iMPACT
4. Select create a new project and follow the instructions on the pictures

Input Handler 8 channel version

Input Handler 8 channel version

Input Handler 8 channel version

Input Handler 8 channel version

Input Handler 8 channel version