FEI4

Features

• Former version (prototype) of chip called FE-I4A
• Better radiation tolerance than the FE-I3
  • >250 MRad
• Digital pixel architecture based on “4-Pixel Digital Region”

• To be fixed in FE-I4
  • DAC ranges to be extended or better centered
  • Generator leakage current
  • More reliable Shift Register read back
  • Properly implement skipped trigger counter

• New functions to be implemented in FE-I4
  • Bunch-Crossing ID counter 13 bits
  • Level 1 Trigger ID counter 12 bits
  • Implement user defined event size limiter for optional long event truncation
  • Tune data format
  • Powering scheme must be tuned to the final IBL powering implementation, using the Shunt-LDO

Parameters

• FE-I4A
  • 130 nm CMOS process
  • 80 x 336 pixel matrix
  • Cell size: 50 μm x 250 μm

Applications

• Under development
• ATLAS installation expected in 2013

-- MarcoBomben - 16-Feb-2012