Notes from Matt

(jones105@purdueNOSPAMPLEASE.edu for details)

For the clock/trigger, we implement everything using two LVDS signals. One is the clock and the other is a serial command signal. Right now it implements four patterns which work even with AC coupled signals. They are IDLE, TRIGGER, HALT and START, and I can provide VHDL that decodes these patterns and sends you a logic signal when they are detected.

In our scheme, we send a HALT on the command line which stops everything, then we asynchronously reset all the counters, and then issue the START command which is guaranteed to start all components of the system in a synchronous fashion. This is how we synchronize our bunch counters among the different FPGA's that are reading out the strips and our DUT's. Let me know if this is what you had in mind and I will dig up the VHDL examples for you. Then we just need to agree on pin mappings.

Sample Firmware

• Top_decoder.vhd
• trigpattern.vhd

-- EricHazen - 2015-08-25