|
aliceSim10 |
atlaSim10 |
atlasGen500 |
atlasReco200 |
cmsDigi100 |
cmsRecoDQM100 |
cmsSim50 |
igwn |
lhcbSim100 |
nsec |
0.3298 |
0.3225 |
0.3170 |
0.3257 |
0.3230 |
0.3223 |
0.3221 |
0.3266 |
0.3159 |
|
cycles |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
|
cycle_activity.cycles_no_execute |
0.3588 |
0.2973 |
0.2959 |
0.3575 |
0.2437 |
0.3055 |
0.3132 |
0.2155 |
0.4392 |
|
icache.ifetch_stall |
0.0783 |
0.0988 |
0.0494 |
0.0346 |
0.0113 |
0.0396 |
0.0913 |
0.0256 |
0.0541 |
|
icache.misses |
0.0102 |
0.0151 |
0.0066 |
0.0037 |
0.0012 |
0.0050 |
0.0134 |
0.0025 |
0.0065 |
|
iTLB-load-misses |
0.0003 |
0.0001 |
0.0001 |
0.0001 |
0.0001 |
0.0001 |
0.0001 |
0.0001 |
0.0003 |
|
iTLB-loads |
0.0025 |
0.0036 |
0.0015 |
0.0005 |
0.0002 |
0.0008 |
0.0023 |
0.0003 |
0.0017 |
|
resource_stalls.any |
0.3214 |
0.2925 |
0.3477 |
0.3695 |
0.2444 |
0.2676 |
0.2875 |
0.3047 |
0.4032 |
|
rs_events.empty_cycles |
0.0945 |
0.0811 |
0.0586 |
0.0728 |
0.0842 |
0.0887 |
0.0850 |
0.0599 |
0.1005 |
|
uops_executed.stall_cycles |
0.3576 |
0.2977 |
0.2957 |
0.3588 |
0.2447 |
0.3064 |
0.3115 |
0.2157 |
0.4396 |
|
uops_executed.cycles_ge_1_uop_exec |
0.6427 |
0.7023 |
0.7041 |
0.6419 |
0.7551 |
0.6935 |
0.6882 |
0.7842 |
0.5602 |
|
uops_executed.cycles_ge_2_uops_exec |
0.4506 |
0.5084 |
0.5092 |
0.4953 |
0.6197 |
0.5244 |
0.4885 |
0.6049 |
0.3418 |
|
uops_executed.cycles_ge_3_uops_exec |
0.2779 |
0.3136 |
0.3131 |
0.3261 |
0.4457 |
0.3456 |
0.2988 |
0.4011 |
0.1945 |
|
uops_executed.cycles_ge_4_uops_exec |
0.1328 |
0.1530 |
0.1472 |
0.1718 |
0.2521 |
0.1815 |
0.1447 |
0.2042 |
0.0908 |
|
instructions |
1.2938 |
1.3642 |
1.4517 |
1.4283 |
1.8104 |
1.4973 |
1.3234 |
2.0335 |
1.0249 |
|
branch-instructions |
0.2224 |
0.1964 |
0.2579 |
0.2173 |
0.3312 |
0.2198 |
0.1994 |
0.3110 |
0.2265 |
|
branch-misses |
0.0036 |
0.0025 |
0.0031 |
0.0035 |
0.0048 |
0.0044 |
0.0038 |
0.0025 |
0.0029 |
|
offcore_requests_outstanding.demand_data_rd_ge_6 |
0.2893 |
0.4262 |
0.2457 |
0.2557 |
0.3504 |
0.4670 |
0.4792 |
0.2480 |
0.2997 |
|
arith.divider_uops |
0.0097 |
0.0153 |
0.0135 |
0.0071 |
0.0067 |
0.0093 |
0.0109 |
0.0138 |
0.0044 |
|
avx_insts.all |
0.0000 |
0.0000 |
0.0000 |
0.0003 |
0.0004 |
0.0021 |
0.0001 |
0.0146 |
0.0000 |
|
mem_load_uops_retired.l1_hit |
0.3568 |
0.4474 |
0.4222 |
0.4054 |
0.5492 |
0.4281 |
0.4288 |
0.3621 |
0.2569 |
|
mem_load_uops_retired.l2_hit |
0.0173 |
0.0199 |
0.0181 |
0.0073 |
0.0031 |
0.0057 |
0.0155 |
0.0033 |
0.0084 |
|
mem_load_uops_retired.l3_hit |
0.0039 |
0.0031 |
0.0065 |
0.0031 |
0.0016 |
0.0023 |
0.0037 |
0.0015 |
0.0530 |
|
mem_load_uops_retired.l3_miss |
0.0002 |
0.0000 |
0.0001 |
0.0008 |
0.0003 |
0.0003 |
0.0001 |
0.0000 |
0.0000 |
|
wall-clock-ns |
0.0869 |
0.0954 |
0.3407 |
0.0946 |
0.0910 |
0.0890 |
0.0851 |
0.1018 |
0.3162 |
|
|
aliceSim10 |
atlaSim10 |
atlasGen500 |
atlasReco200 |
cmsDigi100 |
cmsRecoDQM100 |
cmsSim50 |
igwn |
lhcbSim100 |
nsec |
0.2549 |
0.2364 |
0.2184 |
0.2280 |
0.1784 |
0.2153 |
0.2434 |
0.1606 |
0.3082 |
|
cycles |
0.7729 |
0.7330 |
0.6889 |
0.7001 |
0.5524 |
0.6679 |
0.7556 |
0.4918 |
0.9757 |
|
cycle_activity.cycles_no_execute |
0.2773 |
0.2179 |
0.2038 |
0.2503 |
0.1346 |
0.2040 |
0.2366 |
0.1060 |
0.4286 |
|
icache.ifetch_stall |
0.0605 |
0.0724 |
0.0340 |
0.0242 |
0.0062 |
0.0265 |
0.0690 |
0.0126 |
0.0528 |
|
icache.misses |
0.0079 |
0.0110 |
0.0045 |
0.0026 |
0.0007 |
0.0033 |
0.0102 |
0.0012 |
0.0063 |
|
iTLB-load-misses |
0.0003 |
0.0001 |
0.0001 |
0.0001 |
0.0001 |
0.0001 |
0.0001 |
0.0001 |
0.0003 |
|
iTLB-loads |
0.0020 |
0.0026 |
0.0011 |
0.0003 |
0.0001 |
0.0005 |
0.0018 |
0.0002 |
0.0016 |
|
resource_stalls.any |
0.2484 |
0.2144 |
0.2395 |
0.2587 |
0.1350 |
0.1787 |
0.2172 |
0.1498 |
0.3934 |
|
rs_events.empty_cycles |
0.0730 |
0.0594 |
0.0404 |
0.0509 |
0.0465 |
0.0593 |
0.0642 |
0.0295 |
0.0980 |
|
uops_executed.stall_cycles |
0.2764 |
0.2182 |
0.2037 |
0.2512 |
0.1351 |
0.2047 |
0.2354 |
0.1061 |
0.4289 |
|
uops_executed.cycles_ge_1_uop_exec |
0.4968 |
0.5148 |
0.4851 |
0.4494 |
0.4171 |
0.4632 |
0.5200 |
0.3856 |
0.5465 |
|
uops_executed.cycles_ge_2_uops_exec |
0.3483 |
0.3726 |
0.3508 |
0.3467 |
0.3423 |
0.3502 |
0.3691 |
0.2975 |
0.3334 |
|
uops_executed.cycles_ge_3_uops_exec |
0.2148 |
0.2299 |
0.2157 |
0.2283 |
0.2462 |
0.2308 |
0.2258 |
0.1972 |
0.1898 |
|
uops_executed.cycles_ge_4_uops_exec |
0.1027 |
0.1122 |
0.1014 |
0.1203 |
0.1392 |
0.1212 |
0.1093 |
0.1004 |
0.0886 |
|
instructions |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
|
branch-instructions |
0.1719 |
0.1440 |
0.1777 |
0.1522 |
0.1830 |
0.1468 |
0.1507 |
0.1529 |
0.2210 |
|
branch-misses |
0.0028 |
0.0018 |
0.0021 |
0.0025 |
0.0027 |
0.0030 |
0.0029 |
0.0012 |
0.0029 |
|
offcore_requests_outstanding.demand_data_rd_ge_6 |
0.2236 |
0.3124 |
0.1693 |
0.1790 |
0.1936 |
0.3119 |
0.3621 |
0.1220 |
0.2924 |
|
arith.divider_uops |
0.0075 |
0.0112 |
0.0093 |
0.0050 |
0.0037 |
0.0062 |
0.0083 |
0.0068 |
0.0042 |
|
avx_insts.all |
0.0000 |
0.0000 |
0.0000 |
0.0002 |
0.0002 |
0.0014 |
0.0001 |
0.0072 |
0.0000 |
|
mem_load_uops_retired.l1_hit |
0.2758 |
0.3280 |
0.2909 |
0.2838 |
0.3034 |
0.2859 |
0.3240 |
0.1781 |
0.2507 |
|
mem_load_uops_retired.l2_hit |
0.0133 |
0.0146 |
0.0125 |
0.0051 |
0.0017 |
0.0038 |
0.0117 |
0.0016 |
0.0082 |
|
mem_load_uops_retired.l3_hit |
0.0030 |
0.0023 |
0.0045 |
0.0022 |
0.0009 |
0.0015 |
0.0028 |
0.0007 |
0.0517 |
|
mem_load_uops_retired.l3_miss |
0.0002 |
0.0000 |
0.0001 |
0.0006 |
0.0001 |
0.0002 |
0.0001 |
0.0000 |
0.0000 |
|
wall-clock-ns |
0.0672 |
0.0699 |
0.2347 |
0.0662 |
0.0503 |
0.0595 |
0.0643 |
0.0501 |
0.3085 |
|
|
aliceSim10 |
atlaSim10 |
atlasGen500 |
atlasReco200 |
cmsDigi100 |
cmsRecoDQM100 |
cmsSim50 |
igwn |
lhcbSim100 |
nsec |
3.7936 |
3.3824 |
0.9305 |
3.4441 |
3.5493 |
3.6205 |
3.7861 |
3.2081 |
0.9990 |
|
cycles |
11.5032 |
10.4873 |
2.9351 |
10.5742 |
10.9881 |
11.2319 |
11.7561 |
9.8240 |
3.1623 |
|
cycle_activity.cycles_no_execute |
4.1268 |
3.1179 |
0.8685 |
3.7800 |
2.6774 |
3.4314 |
3.6814 |
2.1173 |
1.3890 |
|
icache.ifetch_stall |
0.9007 |
1.0357 |
0.1449 |
0.3660 |
0.1238 |
0.4450 |
1.0735 |
0.2519 |
0.1711 |
|
icache.misses |
0.1169 |
0.1579 |
0.0192 |
0.0388 |
0.0133 |
0.0560 |
0.1581 |
0.0249 |
0.0205 |
|
iTLB-load-misses |
0.0037 |
0.0014 |
0.0003 |
0.0013 |
0.0014 |
0.0012 |
0.0012 |
0.0014 |
0.0010 |
|
iTLB-loads |
0.0291 |
0.0378 |
0.0045 |
0.0052 |
0.0021 |
0.0089 |
0.0275 |
0.0031 |
0.0053 |
|
resource_stalls.any |
3.6966 |
3.0671 |
1.0205 |
3.9076 |
2.6853 |
3.0054 |
3.3795 |
2.9935 |
1.2751 |
|
rs_events.empty_cycles |
1.0872 |
0.8504 |
0.1721 |
0.7695 |
0.9254 |
0.9968 |
0.9994 |
0.5888 |
0.3177 |
|
uops_executed.stall_cycles |
4.1137 |
3.1217 |
0.8678 |
3.7937 |
2.6883 |
3.4419 |
3.6626 |
2.1191 |
1.3902 |
|
uops_executed.cycles_ge_1_uop_exec |
7.3934 |
7.3652 |
2.0667 |
6.7876 |
8.2975 |
7.7896 |
8.0904 |
7.7040 |
1.7713 |
|
uops_executed.cycles_ge_2_uops_exec |
5.1835 |
5.3313 |
1.4946 |
5.2369 |
6.8090 |
5.8899 |
5.7427 |
5.9424 |
1.0807 |
|
uops_executed.cycles_ge_3_uops_exec |
3.1966 |
3.2889 |
0.9190 |
3.4487 |
4.8973 |
3.8815 |
3.5131 |
3.9400 |
0.6151 |
|
uops_executed.cycles_ge_4_uops_exec |
1.5279 |
1.6051 |
0.4319 |
1.8169 |
2.7700 |
2.0382 |
1.7012 |
2.0065 |
0.2870 |
|
instructions |
14.8833 |
14.3071 |
4.2608 |
15.1036 |
19.8925 |
16.8171 |
15.5580 |
19.9770 |
3.2411 |
|
branch-instructions |
2.5578 |
2.0600 |
0.7571 |
2.2981 |
3.6396 |
2.4690 |
2.3442 |
3.0551 |
0.7163 |
|
branch-misses |
0.0411 |
0.0262 |
0.0091 |
0.0375 |
0.0528 |
0.0498 |
0.0447 |
0.0242 |
0.0093 |
|
offcore_requests_outstanding.demand_data_rd_ge_6 |
3.3284 |
4.4692 |
0.7211 |
2.7034 |
3.8503 |
5.2448 |
5.6335 |
2.4365 |
0.9476 |
|
arith.divider_uops |
0.1115 |
0.1604 |
0.0397 |
0.0754 |
0.0738 |
0.1040 |
0.1284 |
0.1354 |
0.0138 |
|
avx_insts.all |
0.0002 |
0.0000 |
0.0001 |
0.0027 |
0.0045 |
0.0240 |
0.0010 |
0.1434 |
0.0000 |
|
mem_load_uops_retired.l1_hit |
4.1043 |
4.6921 |
1.2393 |
4.2869 |
6.0347 |
4.8088 |
5.0404 |
3.5573 |
0.8125 |
|
mem_load_uops_retired.l2_hit |
0.1987 |
0.2085 |
0.0531 |
0.0769 |
0.0335 |
0.0641 |
0.1818 |
0.0326 |
0.0267 |
|
mem_load_uops_retired.l3_hit |
0.0445 |
0.0325 |
0.0192 |
0.0325 |
0.0174 |
0.0256 |
0.0430 |
0.0148 |
0.1676 |
|
mem_load_uops_retired.l3_miss |
0.0025 |
0.0004 |
0.0004 |
0.0086 |
0.0027 |
0.0031 |
0.0008 |
0.0002 |
0.0001 |
|
wall-clock-ns |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
|
|
aliceSim10 |
atlaSim10 |
atlasGen500 |
atlasReco200 |
cmsDigi100 |
cmsRecoDQM100 |
cmsSim50 |
igwn |
lhcbSim100 |
nsec |
0.3311 |
0.3264 |
0.3201 |
0.3304 |
0.3249 |
0.3268 |
0.3267 |
0.3651 |
0.3213 |
|
cycles |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
|
cycle_activity.stalls_total |
0.3240 |
0.2532 |
0.2601 |
0.3540 |
0.2392 |
0.3024 |
0.2727 |
0.1695 |
0.3761 |
|
cycle_activity.stalls_mem_any |
0.2251 |
0.1678 |
0.2008 |
0.2830 |
0.1464 |
0.2105 |
0.1746 |
0.1074 |
0.3187 |
|
icache_16b.ifdata_stall |
0.0440 |
0.0556 |
0.0311 |
0.0211 |
0.0061 |
0.0187 |
0.0502 |
0.0160 |
0.0462 |
|
iTLB-load-misses |
0.0006 |
0.0001 |
0.0001 |
0.0001 |
0.0001 |
0.0002 |
0.0002 |
0.0001 |
0.0001 |
|
iTLB-loads |
0.0030 |
0.0042 |
0.0017 |
0.0005 |
0.0002 |
0.0008 |
0.0027 |
0.0004 |
0.0026 |
|
rs_events.empty_cycles |
0.0861 |
0.0732 |
0.0571 |
0.0672 |
0.0879 |
0.0819 |
0.0839 |
0.0531 |
0.0536 |
|
uops_executed.stall_cycles |
0.3238 |
0.2532 |
0.2599 |
0.3533 |
0.2390 |
0.3027 |
0.2726 |
0.1693 |
0.3760 |
|
uops_executed.cycles_ge_1_uop_exec |
0.6758 |
0.7464 |
0.7392 |
0.6464 |
0.7605 |
0.6969 |
0.7270 |
0.8304 |
0.6237 |
|
uops_executed.cycles_ge_2_uops_exec |
0.4956 |
0.5729 |
0.5674 |
0.5201 |
0.6346 |
0.5469 |
0.5487 |
0.6744 |
0.3817 |
|
uops_executed.cycles_ge_3_uops_exec |
0.3190 |
0.3816 |
0.3807 |
0.3627 |
0.4721 |
0.3728 |
0.3593 |
0.4867 |
0.2220 |
|
uops_executed.cycles_ge_4_uops_exec |
0.1630 |
0.2051 |
0.2034 |
0.2043 |
0.2879 |
0.2035 |
0.1883 |
0.2803 |
0.1060 |
|
instructions |
1.4435 |
1.5666 |
1.6692 |
1.5407 |
1.9055 |
1.5793 |
1.4983 |
2.3299 |
1.1560 |
|
branch-instructions |
0.2470 |
0.2242 |
0.2877 |
0.2281 |
0.3482 |
0.2288 |
0.2255 |
0.3555 |
0.2597 |
|
branch-misses |
0.0039 |
0.0029 |
0.0034 |
0.0036 |
0.0050 |
0.0045 |
0.0043 |
0.0027 |
0.0033 |
|
arith.divider_active |
0.0753 |
0.1441 |
0.1016 |
0.0536 |
0.0461 |
0.0614 |
0.0979 |
0.1030 |
0.0367 |
|
fp_arith_inst_retired.512b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0013 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.512b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0044 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0002 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.128b_packed_single |
0.0030 |
0.0000 |
0.0000 |
0.0000 |
0.0028 |
0.0226 |
0.0047 |
0.0000 |
0.0018 |
|
fp_arith_inst_retired.128b_packed_double |
0.0016 |
0.0344 |
0.0019 |
0.0792 |
0.0031 |
0.0155 |
0.0242 |
0.0218 |
0.0021 |
|
fp_arith_inst_retired.scalar_single |
0.0242 |
0.0007 |
0.0009 |
0.0233 |
0.0181 |
0.0569 |
0.0073 |
0.0000 |
0.0090 |
|
fp_arith_inst_retired.scalar_double |
0.1358 |
0.2604 |
0.2032 |
0.1236 |
0.1102 |
0.0952 |
0.1789 |
0.2988 |
0.0674 |
|
mem_load_retired.l1_hit |
0.3932 |
0.5103 |
0.4706 |
0.4268 |
0.5804 |
0.4467 |
0.4824 |
0.4167 |
0.2532 |
|
mem_load_retired.l2_hit |
0.0223 |
0.0253 |
0.0233 |
0.0097 |
0.0042 |
0.0075 |
0.0202 |
0.0037 |
0.0311 |
|
mem_load_retired.l3_hit |
0.0008 |
0.0004 |
0.0036 |
0.0009 |
0.0004 |
0.0006 |
0.0009 |
0.0004 |
0.0557 |
|
mem_load_retired.l3_miss |
0.0002 |
0.0001 |
0.0001 |
0.0008 |
0.0002 |
0.0003 |
0.0001 |
0.0000 |
0.0000 |
|
core_power.lvl0_turbo_license |
0.9998 |
0.9998 |
0.9997 |
0.9842 |
0.9979 |
0.9972 |
0.9913 |
0.7707 |
0.9998 |
|
core_power.lvl1_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0153 |
0.0019 |
0.0005 |
0.0085 |
0.1026 |
0.0000 |
|
core_power.lvl2_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0003 |
0.0000 |
0.0021 |
0.0000 |
0.1268 |
0.0000 |
|
wall-clock-ns |
0.0884 |
0.0963 |
0.3279 |
0.1007 |
0.0915 |
0.0924 |
0.0858 |
0.1124 |
0.3214 |
|
|
aliceSim10 |
atlaSim10 |
atlasGen500 |
atlasReco200 |
cmsDigi100 |
cmsRecoDQM100 |
cmsSim50 |
igwn |
lhcbSim100 |
nsec |
0.2294 |
0.2084 |
0.1917 |
0.2145 |
0.1705 |
0.2069 |
0.2181 |
0.1567 |
0.2779 |
|
cycles |
0.6928 |
0.6383 |
0.5991 |
0.6491 |
0.5248 |
0.6332 |
0.6674 |
0.4292 |
0.8650 |
|
cycle_activity.stalls_total |
0.2244 |
0.1617 |
0.1558 |
0.2298 |
0.1255 |
0.1915 |
0.1820 |
0.0728 |
0.3253 |
|
cycle_activity.stalls_mem_any |
0.1560 |
0.1071 |
0.1203 |
0.1837 |
0.0768 |
0.1333 |
0.1166 |
0.0461 |
0.2757 |
|
icache_16b.ifdata_stall |
0.0305 |
0.0355 |
0.0186 |
0.0137 |
0.0032 |
0.0119 |
0.0335 |
0.0068 |
0.0400 |
|
iTLB-load-misses |
0.0004 |
0.0001 |
0.0001 |
0.0001 |
0.0000 |
0.0001 |
0.0001 |
0.0000 |
0.0001 |
|
iTLB-loads |
0.0021 |
0.0027 |
0.0010 |
0.0003 |
0.0001 |
0.0005 |
0.0018 |
0.0002 |
0.0023 |
|
rs_events.empty_cycles |
0.0596 |
0.0467 |
0.0342 |
0.0436 |
0.0462 |
0.0518 |
0.0560 |
0.0228 |
0.0464 |
|
uops_executed.stall_cycles |
0.2243 |
0.1616 |
0.1557 |
0.2293 |
0.1254 |
0.1917 |
0.1819 |
0.0727 |
0.3252 |
|
uops_executed.cycles_ge_1_uop_exec |
0.4682 |
0.4764 |
0.4428 |
0.4196 |
0.3991 |
0.4413 |
0.4852 |
0.3564 |
0.5395 |
|
uops_executed.cycles_ge_2_uops_exec |
0.3433 |
0.3657 |
0.3399 |
0.3376 |
0.3330 |
0.3463 |
0.3662 |
0.2894 |
0.3302 |
|
uops_executed.cycles_ge_3_uops_exec |
0.2210 |
0.2436 |
0.2281 |
0.2354 |
0.2478 |
0.2361 |
0.2398 |
0.2089 |
0.1920 |
|
uops_executed.cycles_ge_4_uops_exec |
0.1129 |
0.1310 |
0.1219 |
0.1326 |
0.1511 |
0.1289 |
0.1256 |
0.1203 |
0.0917 |
|
instructions |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
|
branch-instructions |
0.1711 |
0.1431 |
0.1723 |
0.1480 |
0.1827 |
0.1449 |
0.1505 |
0.1526 |
0.2247 |
|
branch-misses |
0.0027 |
0.0018 |
0.0020 |
0.0024 |
0.0026 |
0.0029 |
0.0028 |
0.0012 |
0.0029 |
|
arith.divider_active |
0.0522 |
0.0920 |
0.0609 |
0.0348 |
0.0242 |
0.0389 |
0.0653 |
0.0442 |
0.0318 |
|
fp_arith_inst_retired.512b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0008 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.512b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0019 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0001 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.128b_packed_single |
0.0021 |
0.0000 |
0.0000 |
0.0000 |
0.0015 |
0.0143 |
0.0031 |
0.0000 |
0.0016 |
|
fp_arith_inst_retired.128b_packed_double |
0.0011 |
0.0220 |
0.0012 |
0.0514 |
0.0016 |
0.0098 |
0.0162 |
0.0094 |
0.0018 |
|
fp_arith_inst_retired.scalar_single |
0.0167 |
0.0004 |
0.0006 |
0.0152 |
0.0095 |
0.0360 |
0.0049 |
0.0000 |
0.0078 |
|
fp_arith_inst_retired.scalar_double |
0.0940 |
0.1662 |
0.1217 |
0.0802 |
0.0578 |
0.0603 |
0.1194 |
0.1282 |
0.0583 |
|
mem_load_retired.l1_hit |
0.2724 |
0.3258 |
0.2819 |
0.2770 |
0.3046 |
0.2828 |
0.3219 |
0.1789 |
0.2190 |
|
mem_load_retired.l2_hit |
0.0154 |
0.0161 |
0.0140 |
0.0063 |
0.0022 |
0.0048 |
0.0135 |
0.0016 |
0.0269 |
|
mem_load_retired.l3_hit |
0.0006 |
0.0002 |
0.0022 |
0.0006 |
0.0002 |
0.0004 |
0.0006 |
0.0002 |
0.0482 |
|
mem_load_retired.l3_miss |
0.0002 |
0.0000 |
0.0001 |
0.0005 |
0.0001 |
0.0002 |
0.0001 |
0.0000 |
0.0000 |
|
core_power.lvl0_turbo_license |
0.6926 |
0.6382 |
0.5989 |
0.6388 |
0.5237 |
0.6314 |
0.6616 |
0.3308 |
0.8648 |
|
core_power.lvl1_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0100 |
0.0010 |
0.0003 |
0.0057 |
0.0440 |
0.0000 |
|
core_power.lvl2_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0002 |
0.0000 |
0.0013 |
0.0000 |
0.0544 |
0.0000 |
|
wall-clock-ns |
0.0612 |
0.0615 |
0.1964 |
0.0653 |
0.0480 |
0.0585 |
0.0572 |
0.0482 |
0.2780 |
|
|
aliceSim10 |
atlaSim10 |
atlasGen500 |
atlasReco200 |
cmsDigi100 |
cmsRecoDQM100 |
cmsSim50 |
igwn |
lhcbSim100 |
nsec |
3.7467 |
3.3893 |
0.9761 |
3.2828 |
3.5498 |
3.5354 |
3.8091 |
3.2485 |
0.9996 |
|
cycles |
11.3170 |
10.3834 |
3.0497 |
9.9348 |
10.9267 |
10.8180 |
11.6587 |
8.8967 |
3.1113 |
|
cycle_activity.stalls_total |
3.6666 |
2.6295 |
0.7931 |
3.5167 |
2.6137 |
3.2713 |
3.1794 |
1.5082 |
1.1702 |
|
cycle_activity.stalls_mem_any |
2.5479 |
1.7419 |
0.6122 |
2.8113 |
1.5997 |
2.2771 |
2.0360 |
0.9559 |
0.9915 |
|
icache_16b.ifdata_stall |
0.4985 |
0.5769 |
0.0948 |
0.2099 |
0.0663 |
0.2028 |
0.5855 |
0.1420 |
0.1438 |
|
iTLB-load-misses |
0.0065 |
0.0009 |
0.0003 |
0.0008 |
0.0007 |
0.0018 |
0.0022 |
0.0010 |
0.0002 |
|
iTLB-loads |
0.0337 |
0.0439 |
0.0051 |
0.0051 |
0.0020 |
0.0087 |
0.0316 |
0.0033 |
0.0082 |
|
rs_events.empty_cycles |
0.9744 |
0.7603 |
0.1740 |
0.6676 |
0.9609 |
0.8857 |
0.9779 |
0.4724 |
0.1668 |
|
uops_executed.stall_cycles |
3.6645 |
2.6286 |
0.7926 |
3.5104 |
2.6111 |
3.2743 |
3.1784 |
1.5064 |
1.1698 |
|
uops_executed.cycles_ge_1_uop_exec |
7.6480 |
7.7501 |
2.2544 |
6.4220 |
8.3101 |
7.5388 |
8.4762 |
7.3879 |
1.9405 |
|
uops_executed.cycles_ge_2_uops_exec |
5.6091 |
5.9487 |
1.7304 |
5.1672 |
6.9337 |
5.9165 |
6.3969 |
5.9997 |
1.1875 |
|
uops_executed.cycles_ge_3_uops_exec |
3.6097 |
3.9623 |
1.1610 |
3.6032 |
5.1590 |
4.0332 |
4.1889 |
4.3302 |
0.6906 |
|
uops_executed.cycles_ge_4_uops_exec |
1.8451 |
2.1301 |
0.6204 |
2.0292 |
3.1461 |
2.2017 |
2.1949 |
2.4934 |
0.3298 |
|
instructions |
16.3363 |
16.2664 |
5.0907 |
15.3062 |
20.8203 |
17.0847 |
17.4688 |
20.7288 |
3.5968 |
|
branch-instructions |
2.7957 |
2.3283 |
0.8773 |
2.2659 |
3.8042 |
2.4750 |
2.6291 |
3.1626 |
0.8082 |
|
branch-misses |
0.0444 |
0.0297 |
0.0104 |
0.0360 |
0.0548 |
0.0492 |
0.0496 |
0.0244 |
0.0103 |
|
arith.divider_active |
0.8523 |
1.4965 |
0.3100 |
0.5325 |
0.5035 |
0.6644 |
1.1410 |
0.9164 |
0.1143 |
|
fp_arith_inst_retired.512b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0002 |
0.0000 |
0.0139 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.512b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0394 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0001 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0016 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.128b_packed_single |
0.0336 |
0.0000 |
0.0001 |
0.0001 |
0.0305 |
0.2447 |
0.0548 |
0.0000 |
0.0057 |
|
fp_arith_inst_retired.128b_packed_double |
0.0179 |
0.3574 |
0.0059 |
0.7869 |
0.0339 |
0.1676 |
0.2823 |
0.1941 |
0.0066 |
|
fp_arith_inst_retired.scalar_single |
0.2734 |
0.0070 |
0.0029 |
0.2319 |
0.1980 |
0.6151 |
0.0855 |
0.0000 |
0.0280 |
|
fp_arith_inst_retired.scalar_double |
1.5363 |
2.7040 |
0.6197 |
1.2281 |
1.2044 |
1.0297 |
2.0860 |
2.6582 |
0.2096 |
|
mem_load_retired.l1_hit |
4.4498 |
5.2990 |
1.4352 |
4.2401 |
6.3420 |
4.8322 |
5.6239 |
3.7075 |
0.7878 |
|
mem_load_retired.l2_hit |
0.2523 |
0.2624 |
0.0710 |
0.0963 |
0.0459 |
0.0812 |
0.2353 |
0.0329 |
0.0968 |
|
mem_load_retired.l3_hit |
0.0096 |
0.0038 |
0.0110 |
0.0086 |
0.0046 |
0.0062 |
0.0101 |
0.0038 |
0.1734 |
|
mem_load_retired.l3_miss |
0.0025 |
0.0006 |
0.0004 |
0.0075 |
0.0019 |
0.0028 |
0.0009 |
0.0001 |
0.0001 |
|
core_power.lvl0_turbo_license |
11.3148 |
10.3815 |
3.0487 |
9.7783 |
10.9042 |
10.7881 |
11.5571 |
6.8564 |
3.1106 |
|
core_power.lvl1_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.1523 |
0.0206 |
0.0057 |
0.0996 |
0.9131 |
0.0000 |
|
core_power.lvl2_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0025 |
0.0000 |
0.0224 |
0.0000 |
1.1284 |
0.0000 |
|
wall-clock-ns |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
|
|
aliceSim10 |
atlaSim10 |
atlasGen500 |
atlasReco200 |
cmsDigi100 |
cmsRecoDQM100 |
cmsSim50 |
igwn |
lhcbSim100 |
nsec |
0.2907 |
0.2898 |
0.2909 |
0.2901 |
0.2898 |
0.2899 |
0.2899 |
0.2962 |
0.2895 |
|
cycles |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
|
cycle_activity.stalls_total |
0.2835 |
0.1975 |
0.2428 |
0.3337 |
0.2306 |
0.2754 |
0.2320 |
0.1583 |
0.3169 |
|
cycle_activity.stalls_mem_any |
0.1934 |
0.1348 |
0.1853 |
0.2626 |
0.1378 |
0.1840 |
0.1486 |
0.1003 |
0.2521 |
|
icache_16b.ifdata_stall |
0.0454 |
0.0519 |
0.0340 |
0.0230 |
0.0071 |
0.0179 |
0.0437 |
0.0177 |
0.0510 |
|
iTLB-load-misses |
0.0008 |
0.0002 |
0.0003 |
0.0001 |
0.0002 |
0.0002 |
0.0004 |
0.0003 |
0.0002 |
|
rs_events.empty_cycles |
0.0772 |
0.0525 |
0.0541 |
0.0668 |
0.0893 |
0.0814 |
0.0682 |
0.0503 |
0.0583 |
|
uops_executed.stall_cycles |
0.2829 |
0.1971 |
0.2427 |
0.3330 |
0.2302 |
0.2748 |
0.2315 |
0.1578 |
0.3162 |
|
uops_executed.cycles_ge_1 |
0.7146 |
0.8006 |
0.7540 |
0.6644 |
0.7674 |
0.7229 |
0.7662 |
0.8396 |
0.6816 |
|
uops_executed.cycles_ge_2 |
0.5533 |
0.6460 |
0.6008 |
0.5547 |
0.6658 |
0.5897 |
0.6033 |
0.7143 |
0.4647 |
|
uops_executed.cycles_ge_3 |
0.3871 |
0.4613 |
0.4335 |
0.4145 |
0.5359 |
0.4310 |
0.4190 |
0.5503 |
0.3045 |
|
uops_executed.cycles_ge_4 |
0.2347 |
0.2876 |
0.2704 |
0.2710 |
0.3743 |
0.2759 |
0.2561 |
0.3657 |
0.1669 |
|
instructions |
1.7547 |
1.8971 |
1.9344 |
1.8036 |
2.2353 |
1.8661 |
1.7731 |
2.6653 |
1.4617 |
|
branch-instructions |
0.2999 |
0.2731 |
0.3436 |
0.2748 |
0.4024 |
0.2739 |
0.2670 |
0.4072 |
0.3301 |
|
branch-misses |
0.0041 |
0.0028 |
0.0032 |
0.0036 |
0.0055 |
0.0049 |
0.0042 |
0.0029 |
0.0036 |
|
arith.divider_active |
0.0905 |
0.1758 |
0.1177 |
0.0658 |
0.0523 |
0.0742 |
0.1151 |
0.1146 |
0.0462 |
|
fp_arith_inst_retired.512b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0016 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.512b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0051 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0002 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.128b_packed_single |
0.0036 |
0.0000 |
0.0001 |
0.0000 |
0.0032 |
0.0272 |
0.0055 |
0.0000 |
0.0023 |
|
fp_arith_inst_retired.128b_packed_double |
0.0019 |
0.0420 |
0.0023 |
0.0960 |
0.0036 |
0.0186 |
0.0287 |
0.0250 |
0.0027 |
|
fp_arith_inst_retired.scalar_single |
0.0294 |
0.0008 |
0.0011 |
0.0282 |
0.0209 |
0.0682 |
0.0087 |
0.0000 |
0.0114 |
|
fp_arith_inst_retired.scalar_double |
0.1661 |
0.3182 |
0.2449 |
0.1502 |
0.1274 |
0.1144 |
0.2122 |
0.3416 |
0.0857 |
|
mem_load_retired.l1_hit |
0.4942 |
0.6463 |
0.5779 |
0.5196 |
0.6751 |
0.5408 |
0.5906 |
0.4809 |
0.3335 |
|
mem_load_retired.l2_hit |
0.0185 |
0.0166 |
0.0195 |
0.0082 |
0.0035 |
0.0057 |
0.0139 |
0.0035 |
0.0620 |
|
mem_load_retired.l3_hit |
0.0009 |
0.0003 |
0.0034 |
0.0009 |
0.0004 |
0.0005 |
0.0008 |
0.0004 |
0.0433 |
|
mem_load_retired.l3_miss |
0.0002 |
0.0000 |
0.0001 |
0.0007 |
0.0002 |
0.0002 |
0.0001 |
0.0000 |
0.0000 |
|
core_power.lvl0_turbo_license |
1.0034 |
1.0032 |
1.0035 |
1.0028 |
1.0032 |
1.0001 |
1.0031 |
0.6407 |
1.0031 |
|
core_power.lvl1_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0001 |
0.0000 |
0.2419 |
0.0000 |
|
core_power.lvl2_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0004 |
0.0000 |
0.0029 |
0.0000 |
0.1204 |
0.0000 |
|
wall-clock-ns |
0.0785 |
0.0853 |
0.2964 |
0.0841 |
0.0833 |
0.0801 |
0.0761 |
0.0911 |
0.2894 |
|
|
aliceSim10 |
atlaSim10 |
atlasGen500 |
atlasReco200 |
cmsDigi100 |
cmsRecoDQM100 |
cmsSim50 |
igwn |
lhcbSim100 |
nsec |
0.1657 |
0.1528 |
0.1504 |
0.1609 |
0.1296 |
0.1553 |
0.1635 |
0.1111 |
0.1981 |
|
cycles |
0.5699 |
0.5271 |
0.5170 |
0.5544 |
0.4474 |
0.5359 |
0.5640 |
0.3752 |
0.6841 |
|
cycle_activity.stalls_total |
0.1616 |
0.1041 |
0.1255 |
0.1850 |
0.1032 |
0.1476 |
0.1308 |
0.0594 |
0.2168 |
|
cycle_activity.stalls_mem_any |
0.1102 |
0.0710 |
0.0958 |
0.1456 |
0.0617 |
0.0986 |
0.0838 |
0.0376 |
0.1725 |
|
icache_16b.ifdata_stall |
0.0259 |
0.0274 |
0.0176 |
0.0128 |
0.0032 |
0.0096 |
0.0247 |
0.0066 |
0.0349 |
|
iTLB-load-misses |
0.0004 |
0.0001 |
0.0001 |
0.0001 |
0.0001 |
0.0001 |
0.0002 |
0.0001 |
0.0001 |
|
rs_events.empty_cycles |
0.0440 |
0.0277 |
0.0280 |
0.0370 |
0.0399 |
0.0436 |
0.0385 |
0.0189 |
0.0399 |
|
uops_executed.stall_cycles |
0.1612 |
0.1039 |
0.1254 |
0.1846 |
0.1030 |
0.1473 |
0.1306 |
0.0592 |
0.2163 |
|
uops_executed.cycles_ge_1 |
0.4072 |
0.4220 |
0.3898 |
0.3684 |
0.3433 |
0.3874 |
0.4321 |
0.3150 |
0.4663 |
|
uops_executed.cycles_ge_2 |
0.3154 |
0.3405 |
0.3106 |
0.3075 |
0.2978 |
0.3160 |
0.3403 |
0.2680 |
0.3179 |
|
uops_executed.cycles_ge_3 |
0.2206 |
0.2431 |
0.2241 |
0.2298 |
0.2397 |
0.2310 |
0.2363 |
0.2065 |
0.2083 |
|
uops_executed.cycles_ge_4 |
0.1338 |
0.1516 |
0.1398 |
0.1502 |
0.1675 |
0.1479 |
0.1444 |
0.1372 |
0.1142 |
|
instructions |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
|
branch-instructions |
0.1709 |
0.1440 |
0.1776 |
0.1523 |
0.1800 |
0.1468 |
0.1506 |
0.1528 |
0.2258 |
|
branch-misses |
0.0023 |
0.0015 |
0.0016 |
0.0020 |
0.0025 |
0.0026 |
0.0023 |
0.0011 |
0.0024 |
|
arith.divider_active |
0.0516 |
0.0927 |
0.0609 |
0.0365 |
0.0234 |
0.0398 |
0.0649 |
0.0430 |
0.0316 |
|
fp_arith_inst_retired.512b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0008 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.512b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0019 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0001 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.128b_packed_single |
0.0021 |
0.0000 |
0.0000 |
0.0000 |
0.0014 |
0.0146 |
0.0031 |
0.0000 |
0.0016 |
|
fp_arith_inst_retired.128b_packed_double |
0.0011 |
0.0221 |
0.0012 |
0.0532 |
0.0016 |
0.0100 |
0.0162 |
0.0094 |
0.0018 |
|
fp_arith_inst_retired.scalar_single |
0.0168 |
0.0004 |
0.0006 |
0.0156 |
0.0093 |
0.0365 |
0.0049 |
0.0000 |
0.0078 |
|
fp_arith_inst_retired.scalar_double |
0.0947 |
0.1677 |
0.1266 |
0.0833 |
0.0570 |
0.0613 |
0.1197 |
0.1282 |
0.0586 |
|
mem_load_retired.l1_hit |
0.2816 |
0.3406 |
0.2987 |
0.2881 |
0.3020 |
0.2898 |
0.3331 |
0.1804 |
0.2282 |
|
mem_load_retired.l2_hit |
0.0105 |
0.0087 |
0.0101 |
0.0045 |
0.0016 |
0.0031 |
0.0078 |
0.0013 |
0.0424 |
|
mem_load_retired.l3_hit |
0.0005 |
0.0001 |
0.0017 |
0.0005 |
0.0002 |
0.0003 |
0.0004 |
0.0001 |
0.0297 |
|
mem_load_retired.l3_miss |
0.0001 |
0.0000 |
0.0001 |
0.0004 |
0.0001 |
0.0001 |
0.0000 |
0.0000 |
0.0000 |
|
core_power.lvl0_turbo_license |
0.5719 |
0.5288 |
0.5188 |
0.5560 |
0.4488 |
0.5359 |
0.5658 |
0.2404 |
0.6863 |
|
core_power.lvl1_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0907 |
0.0000 |
|
core_power.lvl2_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0002 |
0.0000 |
0.0016 |
0.0000 |
0.0452 |
0.0000 |
|
wall-clock-ns |
0.0447 |
0.0449 |
0.1532 |
0.0466 |
0.0373 |
0.0429 |
0.0429 |
0.0342 |
0.1980 |
|
|
aliceSim10 |
atlaSim10 |
atlasGen500 |
atlasReco200 |
cmsDigi100 |
cmsRecoDQM100 |
cmsSim50 |
igwn |
lhcbSim100 |
nsec |
3.7050 |
3.3998 |
0.9814 |
3.4498 |
3.4778 |
3.6208 |
3.8081 |
3.2495 |
1.0005 |
|
cycles |
12.7434 |
11.7297 |
3.3740 |
11.8899 |
12.0006 |
12.4917 |
13.1339 |
10.9721 |
3.4555 |
|
cycle_activity.stalls_total |
3.6127 |
2.3166 |
0.8193 |
3.9672 |
2.7675 |
3.4405 |
3.0464 |
1.7372 |
1.0950 |
|
cycle_activity.stalls_mem_any |
2.4644 |
1.5810 |
0.6251 |
3.1221 |
1.6542 |
2.2987 |
1.9523 |
1.1008 |
0.8710 |
|
icache_16b.ifdata_stall |
0.5781 |
0.6089 |
0.1149 |
0.2736 |
0.0848 |
0.2234 |
0.5743 |
0.1940 |
0.1761 |
|
iTLB-load-misses |
0.0098 |
0.0024 |
0.0009 |
0.0016 |
0.0022 |
0.0029 |
0.0053 |
0.0029 |
0.0005 |
|
rs_events.empty_cycles |
0.9834 |
0.6155 |
0.1825 |
0.7941 |
1.0715 |
1.0162 |
0.8956 |
0.5518 |
0.2013 |
|
uops_executed.stall_cycles |
3.6047 |
2.3120 |
0.8187 |
3.9598 |
2.7623 |
3.4330 |
3.0406 |
1.7311 |
1.0925 |
|
uops_executed.cycles_ge_1 |
9.1061 |
9.3903 |
2.5441 |
7.8999 |
9.2093 |
9.0305 |
10.0626 |
9.2121 |
2.3551 |
|
uops_executed.cycles_ge_2 |
7.0513 |
7.5776 |
2.0272 |
6.5951 |
7.9896 |
7.3667 |
7.9243 |
7.8369 |
1.6059 |
|
uops_executed.cycles_ge_3 |
4.9334 |
5.4104 |
1.4627 |
4.9288 |
6.4310 |
5.3845 |
5.5037 |
6.0378 |
1.0522 |
|
uops_executed.cycles_ge_4 |
2.9914 |
3.3735 |
0.9124 |
3.2221 |
4.4922 |
3.4466 |
3.3630 |
4.0124 |
0.5769 |
|
instructions |
22.3603 |
22.2528 |
6.5267 |
21.4452 |
26.8254 |
23.3110 |
23.2875 |
29.2443 |
5.0509 |
|
branch-instructions |
3.8222 |
3.2034 |
1.1595 |
3.2671 |
4.8294 |
3.4219 |
3.5064 |
4.4673 |
1.1407 |
|
branch-misses |
0.0522 |
0.0325 |
0.0106 |
0.0428 |
0.0663 |
0.0609 |
0.0547 |
0.0319 |
0.0123 |
|
arith.divider_active |
1.1534 |
2.0621 |
0.3972 |
0.7824 |
0.6277 |
0.9275 |
1.5118 |
1.2569 |
0.1598 |
|
fp_arith_inst_retired.512b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0004 |
0.0000 |
0.0197 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.512b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0557 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0001 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0024 |
0.0000 |
0.0000 |
0.0000 |
0.0001 |
0.0000 |
|
fp_arith_inst_retired.128b_packed_single |
0.0460 |
0.0000 |
0.0002 |
0.0002 |
0.0386 |
0.3394 |
0.0728 |
0.0000 |
0.0080 |
|
fp_arith_inst_retired.128b_packed_double |
0.0245 |
0.4927 |
0.0078 |
1.1419 |
0.0438 |
0.2327 |
0.3771 |
0.2747 |
0.0093 |
|
fp_arith_inst_retired.scalar_single |
0.3752 |
0.0097 |
0.0038 |
0.3352 |
0.2504 |
0.8518 |
0.1138 |
0.0000 |
0.0396 |
|
fp_arith_inst_retired.scalar_double |
2.1169 |
3.7326 |
0.8265 |
1.7862 |
1.5285 |
1.4286 |
2.7876 |
3.7483 |
0.2962 |
|
mem_load_retired.l1_hit |
6.2972 |
7.5804 |
1.9498 |
6.1778 |
8.1016 |
6.7550 |
7.7575 |
5.2767 |
1.1524 |
|
mem_load_retired.l2_hit |
0.2351 |
0.1945 |
0.0657 |
0.0971 |
0.0418 |
0.0715 |
0.1820 |
0.0386 |
0.2141 |
|
mem_load_retired.l3_hit |
0.0114 |
0.0033 |
0.0113 |
0.0102 |
0.0049 |
0.0069 |
0.0102 |
0.0044 |
0.1498 |
|
mem_load_retired.l3_miss |
0.0024 |
0.0005 |
0.0005 |
0.0085 |
0.0018 |
0.0026 |
0.0009 |
0.0001 |
0.0001 |
|
core_power.lvl0_turbo_license |
12.7872 |
11.7671 |
3.3858 |
11.9234 |
12.0389 |
12.4932 |
13.1752 |
7.0303 |
3.4664 |
|
core_power.lvl1_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0003 |
0.0000 |
0.0010 |
0.0000 |
2.6538 |
0.0000 |
|
core_power.lvl2_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0052 |
0.0000 |
0.0364 |
0.0000 |
1.3215 |
0.0000 |
|
wall-clock-ns |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
|
|
aliceSim10 |
atlaSim10 |
atlasGen500 |
atlasReco200 |
cmsDigi100 |
cmsRecoDQM100 |
cmsSim10 |
cmsSim50 |
igwn |
lhcbSim100 |
nsec |
0.3896 |
0.3888 |
0.3909 |
0.3890 |
0.3887 |
0.3893 |
0.3888 |
0.3899 |
0.3896 |
0.3906 |
|
cycles |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
|
cycle_activity.cycles_no_execute |
0.4996 |
0.4563 |
0.5203 |
0.4197 |
0.3266 |
0.4006 |
0.4738 |
0.4737 |
0.2872 |
0.6154 |
|
icache.ifetch_stall |
0.0972 |
0.1278 |
0.0484 |
0.0471 |
0.0144 |
0.0600 |
0.1039 |
0.1143 |
0.0253 |
0.0987 |
|
icache.misses |
0.0121 |
0.0188 |
0.0060 |
0.0061 |
0.0018 |
0.0087 |
0.0155 |
0.0171 |
0.0028 |
0.0102 |
|
iTLB-load-misses |
0.0008 |
0.0007 |
0.0003 |
0.0002 |
0.0001 |
0.0002 |
0.0004 |
0.0004 |
0.0001 |
0.0007 |
|
iTLB-loads |
0.0028 |
0.0045 |
0.0021 |
0.0009 |
0.0003 |
0.0012 |
0.0028 |
0.0031 |
0.0004 |
0.0021 |
|
resource_stalls.any |
0.2696 |
0.1988 |
0.3614 |
0.2801 |
0.1673 |
0.1727 |
0.2133 |
0.2042 |
0.2109 |
0.4851 |
|
rs_events.empty_cycles |
0.1198 |
0.1126 |
0.0795 |
0.0860 |
0.0948 |
0.1087 |
0.1318 |
0.1232 |
0.0668 |
0.0920 |
|
uops_executed.stall_cycles |
0.4989 |
0.4561 |
0.5207 |
0.4201 |
0.3271 |
0.4006 |
0.4738 |
0.4736 |
0.2867 |
0.6154 |
|
uops_executed.cycles_ge_1_uop_exec |
0.5011 |
0.5433 |
0.4789 |
0.5798 |
0.6726 |
0.5993 |
0.5261 |
0.5261 |
0.7133 |
0.3846 |
|
uops_executed.cycles_ge_2_uops_exec |
0.2550 |
0.2792 |
0.2417 |
0.3241 |
0.4034 |
0.3251 |
0.2650 |
0.2612 |
0.4437 |
0.1648 |
|
uops_executed.cycles_ge_3_uops_exec |
0.1034 |
0.1127 |
0.0952 |
0.1386 |
0.1844 |
0.1343 |
0.1051 |
0.0999 |
0.2240 |
0.0610 |
|
uops_executed.cycles_ge_4_uops_exec |
0.0314 |
0.0349 |
0.0277 |
0.0444 |
0.0614 |
0.0409 |
0.0318 |
0.0281 |
0.0892 |
0.0163 |
|
instructions |
0.7639 |
0.7857 |
0.7243 |
0.9429 |
1.1401 |
0.9358 |
0.7587 |
0.7490 |
1.4876 |
0.5450 |
|
branch-instructions |
0.1324 |
0.1133 |
0.1289 |
0.1443 |
0.2089 |
0.1376 |
0.1139 |
0.1129 |
0.2274 |
0.1232 |
|
branch-misses |
0.0027 |
0.0022 |
0.0020 |
0.0026 |
0.0031 |
0.0031 |
0.0027 |
0.0027 |
0.0019 |
0.0020 |
|
offcore_requests_outstanding.demand_data_rd_ge_6 |
0.5336 |
0.5411 |
0.5354 |
0.5185 |
0.5265 |
0.5206 |
0.5295 |
0.5421 |
0.4312 |
0.5863 |
|
arith.divider_uops |
0.0056 |
0.0087 |
0.0068 |
0.0045 |
0.0042 |
0.0057 |
0.0066 |
0.0062 |
0.0101 |
0.0022 |
|
avx_insts.all |
0.0000 |
0.0000 |
0.0000 |
0.0002 |
0.0003 |
0.0014 |
0.0006 |
0.0001 |
0.0107 |
0.0000 |
|
mem_load_uops_retired.l1_hit |
0.2061 |
0.2501 |
0.2035 |
0.2667 |
0.3494 |
0.2666 |
0.2326 |
0.2312 |
0.2731 |
0.1290 |
|
mem_load_uops_retired.l2_hit |
0.0076 |
0.0105 |
0.0089 |
0.0046 |
0.0018 |
0.0035 |
0.0083 |
0.0086 |
0.0017 |
0.0048 |
|
mem_load_uops_retired.l3_hit |
0.0022 |
0.0022 |
0.0021 |
0.0014 |
0.0006 |
0.0010 |
0.0019 |
0.0020 |
0.0007 |
0.0186 |
|
mem_load_uops_retired.l3_miss |
0.0001 |
0.0001 |
0.0003 |
0.0002 |
0.0001 |
0.0001 |
0.0001 |
0.0000 |
0.0001 |
0.0004 |
|
wall-clock-ns |
0.0132 |
0.0135 |
0.0134 |
0.0138 |
0.0137 |
0.0132 |
0.0157 |
0.0127 |
0.0174 |
0.0126 |
|
|
aliceSim10 |
atlaSim10 |
atlasGen500 |
atlasReco200 |
cmsDigi100 |
cmsRecoDQM100 |
cmsSim10 |
cmsSim50 |
igwn |
lhcbSim100 |
nsec |
0.5100 |
0.4949 |
0.5397 |
0.4126 |
0.3410 |
0.4160 |
0.5125 |
0.5206 |
0.2619 |
0.7167 |
|
cycles |
1.3091 |
1.2727 |
1.3806 |
1.0605 |
0.8771 |
1.0686 |
1.3181 |
1.3352 |
0.6722 |
1.8348 |
|
cycle_activity.cycles_no_execute |
0.6540 |
0.5807 |
0.7184 |
0.4451 |
0.2865 |
0.4281 |
0.6246 |
0.6324 |
0.1931 |
1.1292 |
|
icache.ifetch_stall |
0.1272 |
0.1627 |
0.0668 |
0.0500 |
0.0126 |
0.0641 |
0.1370 |
0.1526 |
0.0170 |
0.1811 |
|
icache.misses |
0.0159 |
0.0239 |
0.0082 |
0.0065 |
0.0016 |
0.0093 |
0.0204 |
0.0228 |
0.0019 |
0.0187 |
|
iTLB-load-misses |
0.0010 |
0.0009 |
0.0005 |
0.0002 |
0.0001 |
0.0002 |
0.0005 |
0.0006 |
0.0001 |
0.0012 |
|
iTLB-loads |
0.0036 |
0.0057 |
0.0029 |
0.0009 |
0.0003 |
0.0013 |
0.0037 |
0.0041 |
0.0003 |
0.0039 |
|
resource_stalls.any |
0.3529 |
0.2530 |
0.4990 |
0.2971 |
0.1468 |
0.1846 |
0.2812 |
0.2726 |
0.1418 |
0.8900 |
|
rs_events.empty_cycles |
0.1569 |
0.1433 |
0.1098 |
0.0912 |
0.0831 |
0.1162 |
0.1737 |
0.1645 |
0.0449 |
0.1687 |
|
uops_executed.stall_cycles |
0.6531 |
0.5805 |
0.7189 |
0.4455 |
0.2869 |
0.4280 |
0.6245 |
0.6324 |
0.1928 |
1.1292 |
|
uops_executed.cycles_ge_1_uop_exec |
0.6561 |
0.6915 |
0.6612 |
0.6149 |
0.5900 |
0.6404 |
0.6934 |
0.7024 |
0.4795 |
0.7058 |
|
uops_executed.cycles_ge_2_uops_exec |
0.3338 |
0.3553 |
0.3336 |
0.3437 |
0.3538 |
0.3474 |
0.3492 |
0.3487 |
0.2983 |
0.3024 |
|
uops_executed.cycles_ge_3_uops_exec |
0.1353 |
0.1435 |
0.1315 |
0.1470 |
0.1618 |
0.1435 |
0.1386 |
0.1334 |
0.1506 |
0.1119 |
|
uops_executed.cycles_ge_4_uops_exec |
0.0411 |
0.0444 |
0.0382 |
0.0471 |
0.0539 |
0.0437 |
0.0419 |
0.0375 |
0.0600 |
0.0299 |
|
instructions |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
|
branch-instructions |
0.1733 |
0.1441 |
0.1780 |
0.1530 |
0.1832 |
0.1470 |
0.1501 |
0.1507 |
0.1529 |
0.2260 |
|
branch-misses |
0.0035 |
0.0027 |
0.0027 |
0.0027 |
0.0027 |
0.0033 |
0.0035 |
0.0036 |
0.0013 |
0.0038 |
|
offcore_requests_outstanding.demand_data_rd_ge_6 |
0.6985 |
0.6887 |
0.7392 |
0.5499 |
0.4618 |
0.5564 |
0.6980 |
0.7238 |
0.2899 |
1.0758 |
|
arith.divider_uops |
0.0074 |
0.0111 |
0.0094 |
0.0048 |
0.0037 |
0.0061 |
0.0086 |
0.0082 |
0.0068 |
0.0041 |
|
avx_insts.all |
0.0000 |
0.0000 |
0.0000 |
0.0002 |
0.0002 |
0.0015 |
0.0008 |
0.0001 |
0.0072 |
0.0000 |
|
mem_load_uops_retired.l1_hit |
0.2699 |
0.3184 |
0.2809 |
0.2829 |
0.3065 |
0.2848 |
0.3067 |
0.3087 |
0.1836 |
0.2367 |
|
mem_load_uops_retired.l2_hit |
0.0100 |
0.0133 |
0.0123 |
0.0049 |
0.0016 |
0.0037 |
0.0109 |
0.0115 |
0.0012 |
0.0088 |
|
mem_load_uops_retired.l3_hit |
0.0028 |
0.0027 |
0.0029 |
0.0015 |
0.0005 |
0.0011 |
0.0025 |
0.0026 |
0.0005 |
0.0342 |
|
mem_load_uops_retired.l3_miss |
0.0002 |
0.0001 |
0.0004 |
0.0003 |
0.0000 |
0.0001 |
0.0001 |
0.0001 |
0.0000 |
0.0008 |
|
wall-clock-ns |
0.0173 |
0.0172 |
0.0184 |
0.0146 |
0.0120 |
0.0141 |
0.0207 |
0.0170 |
0.0117 |
0.0231 |
|
|
aliceSim10 |
atlaSim10 |
atlasGen500 |
atlasReco200 |
cmsDigi100 |
cmsRecoDQM100 |
cmsSim10 |
cmsSim50 |
igwn |
lhcbSim100 |
nsec |
29.5082 |
28.7105 |
29.2729 |
28.2671 |
28.3977 |
29.5113 |
24.7576 |
30.6286 |
22.4131 |
31.0434 |
|
cycles |
75.7450 |
73.8349 |
74.8824 |
72.6637 |
73.0506 |
75.8115 |
63.6729 |
78.5459 |
57.5265 |
79.4742 |
|
cycle_activity.cycles_no_execute |
37.8419 |
33.6882 |
38.9639 |
30.4956 |
23.8565 |
30.3695 |
30.1696 |
37.2037 |
16.5238 |
48.9107 |
|
icache.ifetch_stall |
7.3589 |
9.4367 |
3.6232 |
3.4241 |
1.0514 |
4.5461 |
6.6172 |
8.9787 |
1.4571 |
7.8451 |
|
icache.misses |
0.9172 |
1.3878 |
0.4469 |
0.4443 |
0.1335 |
0.6578 |
0.9843 |
1.3397 |
0.1599 |
0.8121 |
|
iTLB-load-misses |
0.0598 |
0.0525 |
0.0260 |
0.0133 |
0.0050 |
0.0125 |
0.0264 |
0.0330 |
0.0080 |
0.0522 |
|
iTLB-loads |
0.2100 |
0.3302 |
0.1587 |
0.0638 |
0.0232 |
0.0938 |
0.1802 |
0.2428 |
0.0218 |
0.1702 |
|
resource_stalls.any |
20.4208 |
14.6795 |
27.0657 |
20.3538 |
12.2222 |
13.0948 |
13.5841 |
16.0376 |
12.1307 |
38.5509 |
|
rs_events.empty_cycles |
9.0761 |
8.3111 |
5.9537 |
6.2485 |
6.9232 |
8.2434 |
8.3918 |
9.6767 |
3.8441 |
7.3083 |
|
uops_executed.stall_cycles |
37.7904 |
33.6762 |
38.9892 |
30.5237 |
23.8959 |
30.3676 |
30.1675 |
37.2024 |
16.4957 |
48.9090 |
|
uops_executed.cycles_ge_1_uop_exec |
37.9594 |
40.1161 |
35.8614 |
42.1310 |
49.1358 |
45.4318 |
33.4968 |
41.3201 |
41.0344 |
30.5697 |
|
uops_executed.cycles_ge_2_uops_exec |
19.3150 |
20.6111 |
18.0956 |
23.5489 |
29.4659 |
24.6464 |
16.8703 |
20.5144 |
25.5235 |
13.0998 |
|
uops_executed.cycles_ge_3_uops_exec |
7.8292 |
8.3224 |
7.1320 |
10.0726 |
13.4710 |
10.1796 |
6.6932 |
7.8494 |
12.8886 |
4.8490 |
|
uops_executed.cycles_ge_4_uops_exec |
2.3794 |
2.5765 |
2.0742 |
3.2238 |
4.4879 |
3.1015 |
2.0229 |
2.2051 |
5.1303 |
1.2967 |
|
instructions |
57.8605 |
58.0142 |
54.2380 |
68.5169 |
83.2824 |
70.9456 |
48.3060 |
58.8288 |
85.5754 |
43.3142 |
|
branch-instructions |
10.0287 |
8.3624 |
9.6538 |
10.4856 |
15.2612 |
10.4288 |
7.2522 |
8.8684 |
13.0844 |
9.7885 |
|
branch-misses |
0.2029 |
0.1589 |
0.1468 |
0.1857 |
0.2240 |
0.2314 |
0.1697 |
0.2147 |
0.1095 |
0.1626 |
|
offcore_requests_outstanding.demand_data_rd_ge_6 |
40.4154 |
39.9552 |
40.0918 |
37.6797 |
38.4637 |
39.4711 |
33.7176 |
42.5808 |
24.8042 |
46.5955 |
|
arith.divider_uops |
0.4260 |
0.6411 |
0.5113 |
0.3300 |
0.3093 |
0.4337 |
0.4177 |
0.4835 |
0.5834 |
0.1765 |
|
avx_insts.all |
0.0016 |
0.0008 |
0.0010 |
0.0125 |
0.0207 |
0.1029 |
0.0384 |
0.0041 |
0.6145 |
0.0008 |
|
mem_load_uops_retired.l1_hit |
15.6148 |
18.4693 |
15.2367 |
19.3811 |
25.5220 |
20.2086 |
14.8133 |
18.1595 |
15.7085 |
10.2514 |
|
mem_load_uops_retired.l2_hit |
0.5791 |
0.7726 |
0.6686 |
0.3362 |
0.1307 |
0.2656 |
0.5283 |
0.6778 |
0.0988 |
0.3790 |
|
mem_load_uops_retired.l3_hit |
0.1648 |
0.1589 |
0.1574 |
0.1022 |
0.0415 |
0.0767 |
0.1208 |
0.1536 |
0.0391 |
1.4801 |
|
mem_load_uops_retired.l3_miss |
0.0090 |
0.0043 |
0.0230 |
0.0177 |
0.0039 |
0.0046 |
0.0054 |
0.0038 |
0.0030 |
0.0333 |
|
wall-clock-ns |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
|
|
aliceSim10 |
atlaSim10 |
atlasGen500 |
atlasReco200 |
cmsDigi100 |
cmsRecoDQM100 |
cmsSim10 |
cmsSim50 |
igwn |
lhcbSim100 |
nsec |
0.3730 |
0.3725 |
0.3752 |
0.3742 |
0.3728 |
0.3740 |
0.3724 |
0.3754 |
0.4100 |
0.3794 |
|
cycles |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
|
cycle_activity.stalls_total |
0.3311 |
0.2403 |
0.3468 |
0.3282 |
0.2475 |
0.2840 |
0.2888 |
0.2766 |
0.1752 |
0.4378 |
|
cycle_activity.stalls_mem_any |
0.2444 |
0.1744 |
0.2901 |
0.2621 |
0.1548 |
0.1962 |
0.1819 |
0.1977 |
0.1150 |
0.3795 |
|
icache_16b.ifdata_stall |
0.0444 |
0.0534 |
0.0315 |
0.0227 |
0.0066 |
0.0211 |
0.0428 |
0.0468 |
0.0156 |
0.0547 |
|
iTLB-load-misses |
0.0006 |
0.0001 |
0.0001 |
0.0001 |
0.0001 |
0.0001 |
0.0003 |
0.0002 |
0.0001 |
0.0002 |
|
iTLB-loads |
0.0030 |
0.0043 |
0.0015 |
0.0005 |
0.0002 |
0.0009 |
0.0024 |
0.0026 |
0.0003 |
0.0022 |
|
rs_events.empty_cycles |
0.0751 |
0.0557 |
0.0536 |
0.0632 |
0.0888 |
0.0788 |
0.0834 |
0.0672 |
0.0517 |
0.0546 |
|
uops_executed.stall_cycles |
0.3309 |
0.2402 |
0.3466 |
0.3280 |
0.2473 |
0.2839 |
0.2887 |
0.2765 |
0.1751 |
0.4376 |
|
uops_executed.cycles_ge_1_uop_exec |
0.6685 |
0.7593 |
0.6529 |
0.6715 |
0.7521 |
0.7156 |
0.7108 |
0.7230 |
0.8245 |
0.5619 |
|
uops_executed.cycles_ge_2_uops_exec |
0.4905 |
0.5831 |
0.4956 |
0.5395 |
0.6266 |
0.5608 |
0.5324 |
0.5465 |
0.6699 |
0.3442 |
|
uops_executed.cycles_ge_3_uops_exec |
0.3152 |
0.3878 |
0.3288 |
0.3748 |
0.4657 |
0.3812 |
0.3472 |
0.3575 |
0.4838 |
0.2023 |
|
uops_executed.cycles_ge_4_uops_exec |
0.1610 |
0.2085 |
0.1744 |
0.2112 |
0.2836 |
0.2077 |
0.1824 |
0.1875 |
0.2785 |
0.0948 |
|
instructions |
1.4261 |
1.5878 |
1.4469 |
1.5942 |
1.8798 |
1.6136 |
1.4539 |
1.4859 |
2.3157 |
1.0378 |
|
branch-instructions |
0.2454 |
0.2286 |
0.2573 |
0.2427 |
0.3438 |
0.2367 |
0.2175 |
0.2236 |
0.3536 |
0.2345 |
|
branch-misses |
0.0039 |
0.0029 |
0.0029 |
0.0038 |
0.0049 |
0.0047 |
0.0040 |
0.0042 |
0.0027 |
0.0030 |
|
arith.divider_active |
0.0745 |
0.1472 |
0.0927 |
0.0576 |
0.0458 |
0.0643 |
0.0979 |
0.0977 |
0.1023 |
0.0333 |
|
fp_arith_inst_retired.512b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0014 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.512b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0044 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0002 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.128b_packed_single |
0.0029 |
0.0000 |
0.0000 |
0.0000 |
0.0028 |
0.0238 |
0.0043 |
0.0047 |
0.0000 |
0.0016 |
|
fp_arith_inst_retired.128b_packed_double |
0.0016 |
0.0351 |
0.0017 |
0.0852 |
0.0032 |
0.0162 |
0.0218 |
0.0242 |
0.0218 |
0.0019 |
|
fp_arith_inst_retired.scalar_single |
0.0239 |
0.0007 |
0.0009 |
0.0250 |
0.0180 |
0.0593 |
0.0066 |
0.0073 |
0.0000 |
0.0081 |
|
fp_arith_inst_retired.scalar_double |
0.1341 |
0.2658 |
0.1845 |
0.1331 |
0.1097 |
0.0991 |
0.1800 |
0.1781 |
0.2963 |
0.0608 |
|
mem_load_retired.l1_hit |
0.3895 |
0.5195 |
0.4189 |
0.4526 |
0.5734 |
0.4619 |
0.4622 |
0.4781 |
0.4138 |
0.2356 |
|
mem_load_retired.l2_hit |
0.0220 |
0.0258 |
0.0212 |
0.0101 |
0.0042 |
0.0077 |
0.0188 |
0.0203 |
0.0038 |
0.0312 |
|
mem_load_retired.l3_hit |
0.0006 |
0.0003 |
0.0027 |
0.0006 |
0.0003 |
0.0004 |
0.0006 |
0.0006 |
0.0003 |
0.0463 |
|
mem_load_retired.l3_miss |
0.0004 |
0.0001 |
0.0008 |
0.0011 |
0.0003 |
0.0004 |
0.0002 |
0.0003 |
0.0001 |
0.0003 |
|
core_power.lvl0_turbo_license |
0.9998 |
0.9998 |
0.9998 |
0.9848 |
0.9983 |
0.9973 |
0.9931 |
0.9928 |
0.7679 |
0.9998 |
|
core_power.lvl1_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0147 |
0.0015 |
0.0005 |
0.0066 |
0.0070 |
0.0935 |
0.0000 |
|
core_power.lvl2_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0002 |
0.0000 |
0.0020 |
0.0000 |
0.0000 |
0.1384 |
0.0000 |
|
wall-clock-ns |
0.0131 |
0.0137 |
0.0125 |
0.0138 |
0.0136 |
0.0130 |
0.0169 |
0.0124 |
0.0183 |
0.0122 |
|
|
aliceSim10 |
atlaSim10 |
atlasGen500 |
atlasReco200 |
cmsDigi100 |
cmsRecoDQM100 |
cmsSim10 |
cmsSim50 |
igwn |
lhcbSim100 |
nsec |
0.2615 |
0.2346 |
0.2593 |
0.2347 |
0.1983 |
0.2318 |
0.2561 |
0.2526 |
0.1770 |
0.3656 |
|
cycles |
0.7012 |
0.6298 |
0.6911 |
0.6273 |
0.5320 |
0.6197 |
0.6878 |
0.6730 |
0.4318 |
0.9636 |
|
cycle_activity.stalls_total |
0.2322 |
0.1513 |
0.2397 |
0.2059 |
0.1317 |
0.1760 |
0.1986 |
0.1861 |
0.0757 |
0.4219 |
|
cycle_activity.stalls_mem_any |
0.1713 |
0.1099 |
0.2005 |
0.1644 |
0.0824 |
0.1216 |
0.1251 |
0.1330 |
0.0497 |
0.3656 |
|
icache_16b.ifdata_stall |
0.0311 |
0.0336 |
0.0218 |
0.0142 |
0.0035 |
0.0131 |
0.0294 |
0.0315 |
0.0067 |
0.0527 |
|
iTLB-load-misses |
0.0004 |
0.0001 |
0.0001 |
0.0001 |
0.0000 |
0.0001 |
0.0002 |
0.0001 |
0.0001 |
0.0002 |
|
iTLB-loads |
0.0021 |
0.0027 |
0.0011 |
0.0003 |
0.0001 |
0.0005 |
0.0016 |
0.0017 |
0.0001 |
0.0021 |
|
rs_events.empty_cycles |
0.0527 |
0.0351 |
0.0370 |
0.0396 |
0.0472 |
0.0488 |
0.0574 |
0.0453 |
0.0223 |
0.0526 |
|
uops_executed.stall_cycles |
0.2320 |
0.1513 |
0.2395 |
0.2057 |
0.1315 |
0.1759 |
0.1985 |
0.1861 |
0.0756 |
0.4217 |
|
uops_executed.cycles_ge_1_uop_exec |
0.4688 |
0.4782 |
0.4512 |
0.4212 |
0.4001 |
0.4435 |
0.4889 |
0.4866 |
0.3560 |
0.5414 |
|
uops_executed.cycles_ge_2_uops_exec |
0.3439 |
0.3673 |
0.3425 |
0.3384 |
0.3333 |
0.3476 |
0.3662 |
0.3678 |
0.2893 |
0.3316 |
|
uops_executed.cycles_ge_3_uops_exec |
0.2210 |
0.2442 |
0.2273 |
0.2351 |
0.2478 |
0.2362 |
0.2388 |
0.2406 |
0.2089 |
0.1949 |
|
uops_executed.cycles_ge_4_uops_exec |
0.1129 |
0.1313 |
0.1205 |
0.1325 |
0.1509 |
0.1287 |
0.1255 |
0.1262 |
0.1202 |
0.0913 |
|
instructions |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
|
branch-instructions |
0.1721 |
0.1440 |
0.1778 |
0.1522 |
0.1829 |
0.1467 |
0.1496 |
0.1505 |
0.1527 |
0.2260 |
|
branch-misses |
0.0027 |
0.0018 |
0.0020 |
0.0024 |
0.0026 |
0.0029 |
0.0027 |
0.0028 |
0.0012 |
0.0029 |
|
arith.divider_active |
0.0522 |
0.0927 |
0.0641 |
0.0361 |
0.0244 |
0.0398 |
0.0673 |
0.0658 |
0.0442 |
0.0321 |
|
fp_arith_inst_retired.512b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0008 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.512b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0019 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0001 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.128b_packed_single |
0.0021 |
0.0000 |
0.0000 |
0.0000 |
0.0015 |
0.0147 |
0.0029 |
0.0031 |
0.0000 |
0.0016 |
|
fp_arith_inst_retired.128b_packed_double |
0.0011 |
0.0221 |
0.0012 |
0.0534 |
0.0017 |
0.0100 |
0.0150 |
0.0163 |
0.0094 |
0.0018 |
|
fp_arith_inst_retired.scalar_single |
0.0168 |
0.0004 |
0.0006 |
0.0157 |
0.0096 |
0.0368 |
0.0045 |
0.0049 |
0.0000 |
0.0078 |
|
fp_arith_inst_retired.scalar_double |
0.0940 |
0.1674 |
0.1275 |
0.0835 |
0.0584 |
0.0614 |
0.1238 |
0.1199 |
0.1280 |
0.0586 |
|
mem_load_retired.l1_hit |
0.2731 |
0.3272 |
0.2895 |
0.2839 |
0.3050 |
0.2863 |
0.3179 |
0.3217 |
0.1787 |
0.2270 |
|
mem_load_retired.l2_hit |
0.0154 |
0.0163 |
0.0147 |
0.0064 |
0.0022 |
0.0048 |
0.0129 |
0.0137 |
0.0016 |
0.0301 |
|
mem_load_retired.l3_hit |
0.0004 |
0.0002 |
0.0019 |
0.0004 |
0.0002 |
0.0003 |
0.0004 |
0.0004 |
0.0001 |
0.0446 |
|
mem_load_retired.l3_miss |
0.0003 |
0.0001 |
0.0005 |
0.0007 |
0.0001 |
0.0002 |
0.0002 |
0.0002 |
0.0000 |
0.0002 |
|
core_power.lvl0_turbo_license |
0.7010 |
0.6297 |
0.6909 |
0.6178 |
0.5311 |
0.6180 |
0.6831 |
0.6681 |
0.3316 |
0.9634 |
|
core_power.lvl1_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0092 |
0.0008 |
0.0003 |
0.0046 |
0.0047 |
0.0404 |
0.0000 |
|
core_power.lvl2_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0001 |
0.0000 |
0.0012 |
0.0000 |
0.0000 |
0.0598 |
0.0000 |
|
wall-clock-ns |
0.0092 |
0.0086 |
0.0086 |
0.0087 |
0.0072 |
0.0081 |
0.0116 |
0.0084 |
0.0079 |
0.0117 |
|
|
aliceSim10 |
atlaSim10 |
atlasGen500 |
atlasReco200 |
cmsDigi100 |
cmsRecoDQM100 |
cmsSim10 |
cmsSim50 |
igwn |
lhcbSim100 |
nsec |
28.5603 |
27.1914 |
30.0278 |
27.0540 |
27.4948 |
28.7175 |
22.0192 |
30.1659 |
22.3949 |
31.1684 |
|
cycles |
76.5742 |
72.9897 |
80.0398 |
72.3043 |
73.7567 |
76.7817 |
59.1279 |
80.3592 |
54.6278 |
82.1479 |
|
cycle_activity.stalls_total |
25.3545 |
17.5382 |
27.7598 |
23.7287 |
18.2533 |
21.8095 |
17.0752 |
22.2246 |
9.5717 |
35.9669 |
|
cycle_activity.stalls_mem_any |
18.7120 |
12.7314 |
23.2194 |
18.9481 |
11.4193 |
15.0649 |
10.7572 |
15.8871 |
6.2848 |
31.1716 |
|
icache_16b.ifdata_stall |
3.4013 |
3.8947 |
2.5227 |
1.6415 |
0.4845 |
1.6217 |
2.5280 |
3.7609 |
0.8504 |
4.4954 |
|
iTLB-load-misses |
0.0453 |
0.0090 |
0.0115 |
0.0061 |
0.0056 |
0.0086 |
0.0153 |
0.0171 |
0.0072 |
0.0184 |
|
iTLB-loads |
0.2274 |
0.3111 |
0.1230 |
0.0382 |
0.0129 |
0.0659 |
0.1390 |
0.2075 |
0.0189 |
0.1812 |
|
rs_events.empty_cycles |
5.7529 |
4.0632 |
4.2864 |
4.5686 |
6.5508 |
6.0472 |
4.9330 |
5.4036 |
2.8267 |
4.4835 |
|
uops_executed.stall_cycles |
25.3389 |
17.5312 |
27.7424 |
23.7158 |
18.2386 |
21.7957 |
17.0676 |
22.2160 |
9.5642 |
35.9510 |
|
uops_executed.cycles_ge_1_uop_exec |
51.1930 |
55.4221 |
52.2552 |
48.5503 |
55.4746 |
54.9416 |
42.0302 |
58.1028 |
45.0380 |
46.1572 |
|
uops_executed.cycles_ge_2_uops_exec |
37.5589 |
42.5616 |
39.6663 |
39.0071 |
46.2172 |
43.0622 |
31.4789 |
43.9149 |
36.5957 |
28.2734 |
|
uops_executed.cycles_ge_3_uops_exec |
24.1373 |
28.3036 |
26.3208 |
27.0973 |
34.3507 |
29.2673 |
20.5270 |
28.7318 |
26.4306 |
16.6190 |
|
uops_executed.cycles_ge_4_uops_exec |
12.3273 |
15.2207 |
13.9573 |
15.2742 |
20.9194 |
15.9449 |
10.7861 |
15.0665 |
15.2118 |
7.7843 |
|
instructions |
109.2043 |
115.8926 |
115.8133 |
115.2688 |
138.6450 |
123.8938 |
85.9641 |
119.4080 |
126.5038 |
85.2509 |
|
branch-instructions |
18.7925 |
16.6841 |
20.5910 |
17.5454 |
25.3573 |
18.1727 |
12.8604 |
17.9660 |
19.3154 |
19.2627 |
|
branch-misses |
0.2956 |
0.2141 |
0.2288 |
0.2775 |
0.3602 |
0.3583 |
0.2357 |
0.3354 |
0.1476 |
0.2483 |
|
arith.divider_active |
5.7044 |
10.7451 |
7.4179 |
4.1657 |
3.3783 |
4.9335 |
5.7894 |
7.8524 |
5.5879 |
2.7383 |
|
fp_arith_inst_retired.512b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0019 |
0.0000 |
0.1048 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.512b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.2411 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0007 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0128 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0002 |
0.0000 |
|
fp_arith_inst_retired.128b_packed_single |
0.2252 |
0.0000 |
0.0035 |
0.0011 |
0.2065 |
1.8249 |
0.2530 |
0.3755 |
0.0000 |
0.1352 |
|
fp_arith_inst_retired.128b_packed_double |
0.1194 |
2.5645 |
0.1398 |
6.1598 |
0.2343 |
1.2408 |
1.2909 |
1.9413 |
1.1904 |
0.1564 |
|
fp_arith_inst_retired.scalar_single |
1.8300 |
0.0504 |
0.0681 |
1.8064 |
1.3306 |
4.5546 |
0.3905 |
0.5862 |
0.0000 |
0.6673 |
|
fp_arith_inst_retired.scalar_double |
10.2677 |
19.4031 |
14.7638 |
9.6257 |
8.0943 |
7.6083 |
10.6443 |
14.3133 |
16.1865 |
4.9965 |
|
mem_load_retired.l1_hit |
29.8279 |
37.9158 |
33.5287 |
32.7264 |
42.2917 |
35.4665 |
27.3297 |
38.4186 |
22.6027 |
19.3535 |
|
mem_load_retired.l2_hit |
1.6818 |
1.8850 |
1.6982 |
0.7334 |
0.3096 |
0.5912 |
1.1112 |
1.6348 |
0.2079 |
2.5641 |
|
mem_load_retired.l3_hit |
0.0479 |
0.0227 |
0.2155 |
0.0431 |
0.0246 |
0.0316 |
0.0345 |
0.0504 |
0.0179 |
3.8051 |
|
mem_load_retired.l3_miss |
0.0344 |
0.0090 |
0.0626 |
0.0790 |
0.0202 |
0.0298 |
0.0146 |
0.0250 |
0.0050 |
0.0211 |
|
core_power.lvl0_turbo_license |
76.5564 |
72.9725 |
80.0202 |
71.2087 |
73.6325 |
76.5715 |
58.7179 |
79.7803 |
41.9478 |
82.1345 |
|
core_power.lvl1_turbo_license |
0.0000 |
0.0000 |
0.0008 |
1.0641 |
0.1087 |
0.0415 |
0.3925 |
0.5623 |
5.1104 |
0.0000 |
|
core_power.lvl2_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0161 |
0.0000 |
0.1509 |
0.0000 |
0.0000 |
7.5619 |
0.0000 |
|
wall-clock-ns |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
|
|
aliceSim10 |
atlaSim10 |
atlasGen500 |
atlasReco200 |
cmsDigi100 |
cmsRecoDQM100 |
cmsSim10 |
cmsSim50 |
igwn |
lhcbSim100 |
nsec |
0.3062 |
0.3068 |
0.3081 |
0.3062 |
0.3060 |
0.3063 |
0.3058 |
0.3071 |
0.3056 |
0.3067 |
|
cycles |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
|
cycle_activity.stalls_total |
0.3177 |
0.2117 |
0.3233 |
0.3288 |
0.2561 |
0.2801 |
0.2869 |
0.2658 |
0.1681 |
0.3931 |
|
cycle_activity.stalls_mem_any |
0.2255 |
0.1487 |
0.2678 |
0.2586 |
0.1567 |
0.1861 |
0.1693 |
0.1816 |
0.1092 |
0.3271 |
|
icache_16b.ifdata_stall |
0.0443 |
0.0515 |
0.0370 |
0.0279 |
0.0082 |
0.0233 |
0.0388 |
0.0428 |
0.0176 |
0.0585 |
|
iTLB-load-misses |
0.0007 |
0.0002 |
0.0003 |
0.0001 |
0.0002 |
0.0002 |
0.0005 |
0.0004 |
0.0003 |
0.0002 |
|
rs_events.empty_cycles |
0.0798 |
0.0529 |
0.0514 |
0.0666 |
0.0980 |
0.0840 |
0.0897 |
0.0689 |
0.0517 |
0.0597 |
|
uops_executed.stall_cycles |
0.3170 |
0.2113 |
0.3226 |
0.3280 |
0.2554 |
0.2795 |
0.2863 |
0.2652 |
0.1677 |
0.3923 |
|
uops_executed.cycles_ge_1 |
0.6804 |
0.7863 |
0.6747 |
0.6695 |
0.7421 |
0.7181 |
0.7111 |
0.7323 |
0.8297 |
0.6052 |
|
uops_executed.cycles_ge_2 |
0.5251 |
0.6332 |
0.5339 |
0.5587 |
0.6423 |
0.5849 |
0.5522 |
0.5754 |
0.7057 |
0.4083 |
|
uops_executed.cycles_ge_3 |
0.3666 |
0.4518 |
0.3844 |
0.4174 |
0.5165 |
0.4273 |
0.3806 |
0.3993 |
0.5433 |
0.2694 |
|
uops_executed.cycles_ge_4 |
0.2222 |
0.2815 |
0.2389 |
0.2729 |
0.3620 |
0.2737 |
0.2319 |
0.2443 |
0.3606 |
0.1473 |
|
instructions |
1.6638 |
1.8561 |
1.7187 |
1.8188 |
2.1544 |
1.8514 |
1.6297 |
1.6898 |
2.6284 |
1.2868 |
|
branch-instructions |
0.2859 |
0.2672 |
0.3056 |
0.2768 |
0.3942 |
0.2716 |
0.2459 |
0.2544 |
0.4017 |
0.2908 |
|
branch-misses |
0.0039 |
0.0026 |
0.0026 |
0.0036 |
0.0053 |
0.0048 |
0.0040 |
0.0039 |
0.0029 |
0.0031 |
|
arith.divider_active |
0.0860 |
0.1724 |
0.1065 |
0.0669 |
0.0517 |
0.0742 |
0.1093 |
0.1103 |
0.1127 |
0.0409 |
|
fp_arith_inst_retired.512b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0016 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.512b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0050 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0002 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.128b_packed_single |
0.0035 |
0.0000 |
0.0001 |
0.0000 |
0.0032 |
0.0272 |
0.0048 |
0.0053 |
0.0000 |
0.0020 |
|
fp_arith_inst_retired.128b_packed_double |
0.0018 |
0.0411 |
0.0021 |
0.0974 |
0.0036 |
0.0186 |
0.0246 |
0.0274 |
0.0248 |
0.0024 |
|
fp_arith_inst_retired.scalar_single |
0.0281 |
0.0008 |
0.0010 |
0.0285 |
0.0207 |
0.0682 |
0.0075 |
0.0083 |
0.0000 |
0.0101 |
|
fp_arith_inst_retired.scalar_double |
0.1576 |
0.3116 |
0.2196 |
0.1523 |
0.1259 |
0.1140 |
0.2030 |
0.2027 |
0.3353 |
0.0756 |
|
mem_load_retired.l1_hit |
0.4699 |
0.6328 |
0.5130 |
0.5247 |
0.6612 |
0.5369 |
0.5385 |
0.5635 |
0.4736 |
0.3002 |
|
mem_load_retired.l2_hit |
0.0176 |
0.0160 |
0.0174 |
0.0081 |
0.0034 |
0.0057 |
0.0121 |
0.0132 |
0.0034 |
0.0576 |
|
mem_load_retired.l3_hit |
0.0006 |
0.0002 |
0.0025 |
0.0006 |
0.0003 |
0.0004 |
0.0005 |
0.0005 |
0.0003 |
0.0340 |
|
mem_load_retired.l3_miss |
0.0004 |
0.0001 |
0.0007 |
0.0010 |
0.0002 |
0.0003 |
0.0002 |
0.0003 |
0.0001 |
0.0002 |
|
core_power.lvl0_turbo_license |
1.0036 |
1.0035 |
1.0037 |
1.0033 |
1.0034 |
1.0006 |
1.0036 |
1.0037 |
0.6616 |
1.0036 |
|
core_power.lvl1_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0001 |
0.0000 |
0.0000 |
0.2223 |
0.0000 |
|
core_power.lvl2_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0005 |
0.0000 |
0.0029 |
0.0000 |
0.0000 |
0.1208 |
0.0000 |
|
wall-clock-ns |
0.0108 |
0.0113 |
0.0102 |
0.0114 |
0.0110 |
0.0107 |
0.0120 |
0.0102 |
0.0146 |
0.0101 |
|
|
aliceSim10 |
atlaSim10 |
atlasGen500 |
atlasReco200 |
cmsDigi100 |
cmsRecoDQM100 |
cmsSim10 |
cmsSim50 |
igwn |
lhcbSim100 |
nsec |
0.1841 |
0.1653 |
0.1793 |
0.1684 |
0.1420 |
0.1654 |
0.1876 |
0.1817 |
0.1163 |
0.2383 |
|
cycles |
0.6010 |
0.5388 |
0.5818 |
0.5498 |
0.4642 |
0.5401 |
0.6136 |
0.5918 |
0.3805 |
0.7771 |
|
cycle_activity.stalls_total |
0.1909 |
0.1140 |
0.1881 |
0.1808 |
0.1189 |
0.1513 |
0.1760 |
0.1573 |
0.0640 |
0.3055 |
|
cycle_activity.stalls_mem_any |
0.1355 |
0.0801 |
0.1558 |
0.1422 |
0.0727 |
0.1005 |
0.1039 |
0.1075 |
0.0416 |
0.2542 |
|
icache_16b.ifdata_stall |
0.0266 |
0.0278 |
0.0215 |
0.0153 |
0.0038 |
0.0126 |
0.0238 |
0.0253 |
0.0067 |
0.0455 |
|
iTLB-load-misses |
0.0004 |
0.0001 |
0.0001 |
0.0001 |
0.0001 |
0.0001 |
0.0003 |
0.0002 |
0.0001 |
0.0001 |
|
rs_events.empty_cycles |
0.0480 |
0.0285 |
0.0299 |
0.0366 |
0.0455 |
0.0454 |
0.0551 |
0.0407 |
0.0197 |
0.0464 |
|
uops_executed.stall_cycles |
0.1905 |
0.1138 |
0.1877 |
0.1804 |
0.1186 |
0.1510 |
0.1757 |
0.1569 |
0.0638 |
0.3049 |
|
uops_executed.cycles_ge_1 |
0.4090 |
0.4237 |
0.3925 |
0.3681 |
0.3445 |
0.3878 |
0.4364 |
0.4334 |
0.3156 |
0.4703 |
|
uops_executed.cycles_ge_2 |
0.3156 |
0.3411 |
0.3107 |
0.3072 |
0.2981 |
0.3159 |
0.3388 |
0.3405 |
0.2685 |
0.3173 |
|
uops_executed.cycles_ge_3 |
0.2203 |
0.2434 |
0.2236 |
0.2295 |
0.2397 |
0.2308 |
0.2335 |
0.2363 |
0.2067 |
0.2094 |
|
uops_executed.cycles_ge_4 |
0.1335 |
0.1517 |
0.1390 |
0.1500 |
0.1680 |
0.1479 |
0.1423 |
0.1446 |
0.1372 |
0.1145 |
|
instructions |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
|
branch-instructions |
0.1718 |
0.1440 |
0.1778 |
0.1522 |
0.1830 |
0.1467 |
0.1509 |
0.1505 |
0.1528 |
0.2260 |
|
branch-misses |
0.0023 |
0.0014 |
0.0015 |
0.0020 |
0.0025 |
0.0026 |
0.0024 |
0.0023 |
0.0011 |
0.0024 |
|
arith.divider_active |
0.0517 |
0.0929 |
0.0619 |
0.0368 |
0.0240 |
0.0401 |
0.0671 |
0.0653 |
0.0429 |
0.0318 |
|
fp_arith_inst_retired.512b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0009 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.512b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0019 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0001 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.128b_packed_single |
0.0021 |
0.0000 |
0.0000 |
0.0000 |
0.0015 |
0.0147 |
0.0030 |
0.0031 |
0.0000 |
0.0016 |
|
fp_arith_inst_retired.128b_packed_double |
0.0011 |
0.0222 |
0.0012 |
0.0535 |
0.0017 |
0.0100 |
0.0151 |
0.0162 |
0.0094 |
0.0018 |
|
fp_arith_inst_retired.scalar_single |
0.0169 |
0.0004 |
0.0006 |
0.0157 |
0.0096 |
0.0368 |
0.0046 |
0.0049 |
0.0000 |
0.0078 |
|
fp_arith_inst_retired.scalar_double |
0.0947 |
0.1679 |
0.1278 |
0.0838 |
0.0584 |
0.0616 |
0.1245 |
0.1200 |
0.1276 |
0.0588 |
|
mem_load_retired.l1_hit |
0.2824 |
0.3409 |
0.2985 |
0.2885 |
0.3069 |
0.2900 |
0.3304 |
0.3335 |
0.1802 |
0.2333 |
|
mem_load_retired.l2_hit |
0.0106 |
0.0086 |
0.0101 |
0.0045 |
0.0016 |
0.0031 |
0.0075 |
0.0078 |
0.0013 |
0.0448 |
|
mem_load_retired.l3_hit |
0.0004 |
0.0001 |
0.0015 |
0.0003 |
0.0001 |
0.0002 |
0.0003 |
0.0003 |
0.0001 |
0.0265 |
|
mem_load_retired.l3_miss |
0.0003 |
0.0001 |
0.0004 |
0.0005 |
0.0001 |
0.0002 |
0.0001 |
0.0002 |
0.0000 |
0.0002 |
|
core_power.lvl0_turbo_license |
0.6032 |
0.5407 |
0.5840 |
0.5516 |
0.4658 |
0.5405 |
0.6158 |
0.5940 |
0.2517 |
0.7799 |
|
core_power.lvl1_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0846 |
0.0000 |
|
core_power.lvl2_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0002 |
0.0000 |
0.0016 |
0.0000 |
0.0000 |
0.0460 |
0.0000 |
|
wall-clock-ns |
0.0065 |
0.0061 |
0.0060 |
0.0063 |
0.0051 |
0.0058 |
0.0074 |
0.0060 |
0.0056 |
0.0078 |
|
|
aliceSim10 |
atlaSim10 |
atlasGen500 |
atlasReco200 |
cmsDigi100 |
cmsRecoDQM100 |
cmsSim10 |
cmsSim50 |
igwn |
lhcbSim100 |
nsec |
28.3732 |
27.1643 |
30.0950 |
26.8214 |
27.7001 |
28.6282 |
25.4866 |
30.0646 |
20.8779 |
30.4618 |
|
cycles |
92.6474 |
88.5405 |
97.6819 |
87.5876 |
90.5267 |
93.4678 |
83.3419 |
97.9008 |
68.3244 |
99.3275 |
|
cycle_activity.stalls_total |
29.4302 |
18.7422 |
31.5777 |
28.7975 |
23.1861 |
26.1817 |
23.9077 |
26.0193 |
11.4878 |
39.0470 |
|
cycle_activity.stalls_mem_any |
20.8919 |
13.1624 |
26.1569 |
22.6480 |
14.1819 |
17.3931 |
14.1092 |
17.7768 |
7.4623 |
32.4873 |
|
icache_16b.ifdata_stall |
4.1067 |
4.5614 |
3.6145 |
2.4432 |
0.7440 |
2.1793 |
3.2329 |
4.1927 |
1.2050 |
5.8121 |
|
iTLB-load-misses |
0.0687 |
0.0191 |
0.0252 |
0.0105 |
0.0164 |
0.0219 |
0.0433 |
0.0394 |
0.0172 |
0.0191 |
|
rs_events.empty_cycles |
7.3954 |
4.6818 |
5.0191 |
5.8339 |
8.8721 |
7.8496 |
7.4796 |
6.7406 |
3.5342 |
5.9330 |
|
uops_executed.stall_cycles |
29.3717 |
18.7047 |
31.5144 |
28.7317 |
23.1232 |
26.1244 |
23.8620 |
25.9617 |
11.4553 |
38.9675 |
|
uops_executed.cycles_ge_1 |
63.0419 |
69.6232 |
65.9047 |
58.6371 |
67.1835 |
67.1152 |
59.2671 |
71.6961 |
56.6855 |
60.1132 |
|
uops_executed.cycles_ge_2 |
48.6483 |
56.0615 |
52.1564 |
48.9344 |
58.1415 |
54.6669 |
46.0202 |
56.3295 |
48.2156 |
40.5586 |
|
uops_executed.cycles_ge_3 |
33.9637 |
39.9996 |
37.5444 |
36.5616 |
46.7564 |
39.9406 |
31.7170 |
39.0949 |
37.1239 |
26.7621 |
|
uops_executed.cycles_ge_4 |
20.5828 |
24.9285 |
23.3408 |
23.9023 |
32.7668 |
25.5858 |
19.3274 |
23.9182 |
24.6386 |
14.6314 |
|
instructions |
154.1445 |
164.3413 |
167.8899 |
159.3067 |
195.0304 |
173.0480 |
135.8212 |
165.4287 |
179.5868 |
127.8163 |
|
branch-instructions |
26.4861 |
23.6586 |
29.8471 |
24.2461 |
35.6835 |
25.3853 |
20.4930 |
24.9026 |
27.4447 |
28.8838 |
|
branch-misses |
0.3587 |
0.2336 |
0.2502 |
0.3132 |
0.4794 |
0.4452 |
0.3307 |
0.3847 |
0.1983 |
0.3106 |
|
arith.divider_active |
7.9634 |
15.2650 |
10.4005 |
5.8581 |
4.6799 |
6.9375 |
9.1098 |
10.7967 |
7.7011 |
4.0629 |
|
fp_arith_inst_retired.512b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0026 |
0.0000 |
0.1499 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.512b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.3412 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_single |
0.0000 |
0.0000 |
0.0000 |
0.0010 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
|
fp_arith_inst_retired.256b_packed_double |
0.0000 |
0.0000 |
0.0000 |
0.0178 |
0.0000 |
0.0000 |
0.0000 |
0.0000 |
0.0003 |
0.0000 |
|
fp_arith_inst_retired.128b_packed_single |
0.3198 |
0.0000 |
0.0051 |
0.0015 |
0.2908 |
2.5465 |
0.4020 |
0.5198 |
0.0000 |
0.2031 |
|
fp_arith_inst_retired.128b_packed_double |
0.1697 |
3.6425 |
0.2029 |
8.5274 |
0.3281 |
1.7346 |
2.0520 |
2.6867 |
1.6953 |
0.2351 |
|
fp_arith_inst_retired.scalar_single |
2.6005 |
0.0716 |
0.0989 |
2.4985 |
1.8728 |
6.3706 |
0.6209 |
0.8115 |
0.0000 |
1.0029 |
|
fp_arith_inst_retired.scalar_double |
14.6030 |
27.5858 |
21.4513 |
13.3434 |
11.3992 |
10.6531 |
16.9147 |
19.8481 |
22.9114 |
7.5127 |
|
mem_load_retired.l1_hit |
43.5379 |
56.0263 |
50.1073 |
45.9556 |
59.8591 |
50.1815 |
44.8806 |
55.1648 |
32.3586 |
29.8182 |
|
mem_load_retired.l2_hit |
1.6288 |
1.4175 |
1.7019 |
0.7115 |
0.3059 |
0.5302 |
1.0123 |
1.2894 |
0.2345 |
5.7233 |
|
mem_load_retired.l3_hit |
0.0579 |
0.0189 |
0.2456 |
0.0513 |
0.0277 |
0.0355 |
0.0382 |
0.0490 |
0.0212 |
3.3812 |
|
mem_load_retired.l3_miss |
0.0402 |
0.0103 |
0.0699 |
0.0876 |
0.0226 |
0.0322 |
0.0197 |
0.0291 |
0.0054 |
0.0228 |
|
core_power.lvl0_turbo_license |
92.9845 |
88.8516 |
98.0475 |
87.8736 |
90.8385 |
93.5279 |
83.6415 |
98.2628 |
45.2029 |
99.6844 |
|
core_power.lvl1_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0029 |
0.0001 |
0.0080 |
0.0000 |
0.0000 |
15.1872 |
0.0000 |
|
core_power.lvl2_turbo_license |
0.0000 |
0.0000 |
0.0000 |
0.0395 |
0.0000 |
0.2685 |
0.0000 |
0.0000 |
8.2562 |
0.0000 |
|
wall-clock-ns |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
1.0000 |
|