Haswell | IvyBridge | ||||||||||
CMS tkreco 6 | CMS sim 6 | CMS sim 1 | HSPEC 6 | HSPEC 1 | CMS tkreco 6 | CMS sim 6 | CMS sim 1 | HSPEC 6 | HSPEC 1 | ||
cycles | 1.0000 | 1.0000 | 1.0000 | 1.0000 | 1.0000 | 1.0000 | 1.0000 | 1.0000 | 1.0000 | 1.0000 | |
instructions | 1.6311 | 1.3068 | 1.3557 | 1.3905 | 1.6171 | 1.3133 | 0.7024 | 0.8056 | 1.2572 | 1.4696 | |
branch-instructions | 0.2130 | 0.1719 | 0.1772 | 0.2285 | 0.2695 | 0.1716 | 0.0931 | 0.1052 | 0.2065 | 0.2449 | |
branch-misses | 0.0031 | 0.0035 | 0.0034 | 0.0057 | 0.0068 | 0.0025 | 0.0021 | 0.0023 | 0.0054 | 0.0065 | |
cycle_activity_cycles_no_execute | 0.2354 | 0.2932 | 0.2755 | 0.3645 | 0.2671 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | |
icache_ifetch_stall | 0.0198 | 0.0447 | 0.0412 | 0.0047 | 0.0080 | 0.1131 | 0.1368 | 0.1347 | 0.0158 | 0.0254 | |
icache_misses | 0.0029 | 0.0068 | 0.0065 | 0.0005 | 0.0009 | 0.0114 | 0.0126 | 0.0138 | 0.0014 | 0.0024 | |
mem_load_uops_retired_l1_hit | 0.4250 | 0.3999 | 0.4197 | 0.3641 | 0.4238 | 0.3435 | 0.2147 | 0.2493 | 0.3315 | 0.3884 | |
mem_load_uops_retired_l2_hit | 0.0061 | 0.0096 | 0.0097 | 0.0085 | 0.0095 | 0.0046 | 0.0051 | 0.0056 | 0.0070 | 0.0082 | |
mem_load_uops_retired_l3_hit | 0.0056 | 0.0021 | 0.0023 | 0.0037 | 0.0055 | 0.0048 | 0.0015 | 0.0015 | 0.0041 | 0.0060 | |
mem_load_uops_retired_l3_miss | 0.0001 | 0.0001 | 0.0000 | 0.0018 | 0.0006 | 0.0001 | 0.0000 | 0.0000 | 0.0014 | 0.0004 | |
offcore_requests_outstanding_demand_data_rd_ge_6 | 0.5377 | 0.6101 | 0.5866 | 0.6663 | 0.1491 | 0.0078 | 0.0006 | 0.0006 | 0.2532 | 0.0116 | |
resource_stalls_any | 0.3745 | 0.4113 | 0.4138 | 0.4137 | 0.3044 | 0.3378 | 0.5097 | 0.4747 | 0.4260 | 0.3088 | |
rs_events_empty_cycles | 0.0392 | 0.0862 | 0.0713 | 0.0722 | 0.0699 | 0.0767 | 0.3919 | 0.3188 | 0.0719 | 0.0729 | |
uops_executed_cycles_ge_1_uop_exec | 0.7635 | 0.7060 | 0.7213 | 0.6345 | 0.7323 | 0.6903 | 0.4266 | 0.4824 | 0.6303 | 0.7322 | |
uops_executed_cycles_ge_2_uops_exec | 0.5478 | 0.4948 | 0.5052 | 0.4974 | 0.5781 | 0.4662 | 0.2789 | 0.3160 | 0.4753 | 0.5550 | |
uops_executed_cycles_ge_3_uops_exec | 0.3440 | 0.3055 | 0.3135 | 0.3353 | 0.3907 | 0.2625 | 0.1540 | 0.1740 | 0.2942 | 0.3446 | |
uops_executed_cycles_ge_4_uops_exec | 0.1789 | 0.1588 | 0.1623 | 0.1793 | 0.2093 | 0.1069 | 0.0620 | 0.0702 | 0.1303 | 0.1531 | |
uops_executed_stall_cycles | 0.2357 | 0.2933 | 0.2779 | 0.3648 | 0.2674 | 0.3103 | 0.5742 | 0.5186 | 0.3704 | 0.2683 | |
arith_divider_uops | 0.0140 | 0.0120 | 0.0147 | 0.0009 | 0.0011 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
Haswell | IvyBridge | ||||||||||
CMS tkreco 6 | CMS sim 6 | CMS sim 1 | HSPEC 6 | HSPEC 1 | CMS tkreco 6 | CMS sim 6 | CMS sim 1 | HSPEC 6 | HSPEC 1 | ||
instructions | 1.0000 | 1.0000 | 1.0000 | 1.0000 | 1.0000 | 1.0000 | 1.0000 | 1.0000 | 1.0000 | 1.0000 | |
cycles | 0.6131 | 0.7652 | 0.7376 | 0.7192 | 0.6184 | 0.7615 | 1.4237 | 1.2413 | 0.7954 | 0.6804 | |
branch-instructions | 0.1306 | 0.1315 | 0.1307 | 0.1643 | 0.1667 | 0.1306 | 0.1325 | 0.1306 | 0.1643 | 0.1666 | |
branch-misses | 0.0019 | 0.0026 | 0.0025 | 0.0041 | 0.0042 | 0.0019 | 0.0030 | 0.0029 | 0.0043 | 0.0044 | |
cycle_activity_cycles_no_execute | 0.1443 | 0.2244 | 0.2032 | 0.2622 | 0.1652 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | |
icache_ifetch_stall | 0.0121 | 0.0342 | 0.0304 | 0.0034 | 0.0049 | 0.0861 | 0.1947 | 0.1672 | 0.0126 | 0.0173 | |
icache_misses | 0.0018 | 0.0052 | 0.0048 | 0.0003 | 0.0006 | 0.0086 | 0.0179 | 0.0171 | 0.0011 | 0.0017 | |
mem_load_uops_retired_l1_hit | 0.2606 | 0.3060 | 0.3096 | 0.2619 | 0.2621 | 0.2616 | 0.3057 | 0.3094 | 0.2637 | 0.2643 | |
mem_load_uops_retired_l2_hit | 0.0037 | 0.0073 | 0.0072 | 0.0061 | 0.0059 | 0.0035 | 0.0073 | 0.0069 | 0.0056 | 0.0056 | |
mem_load_uops_retired_l3_hit | 0.0034 | 0.0016 | 0.0017 | 0.0027 | 0.0034 | 0.0036 | 0.0021 | 0.0019 | 0.0032 | 0.0041 | |
mem_load_uops_retired_l3_miss | 0.0001 | 0.0001 | 0.0000 | 0.0013 | 0.0004 | 0.0001 | 0.0000 | 0.0000 | 0.0011 | 0.0002 | |
offcore_requests_outstanding_demand_data_rd_ge_6 | 0.3297 | 0.4668 | 0.4327 | 0.4792 | 0.0922 | 0.0060 | 0.0008 | 0.0008 | 0.2014 | 0.0079 | |
resource_stalls_any | 0.2296 | 0.3147 | 0.3052 | 0.2976 | 0.1882 | 0.2572 | 0.7257 | 0.5892 | 0.3389 | 0.2102 | |
rs_events_empty_cycles | 0.0240 | 0.0660 | 0.0526 | 0.0519 | 0.0432 | 0.0584 | 0.5580 | 0.3957 | 0.0572 | 0.0496 | |
uops_executed_cycles_ge_1_uop_exec | 0.4681 | 0.5403 | 0.5321 | 0.4563 | 0.4528 | 0.5256 | 0.6074 | 0.5988 | 0.5014 | 0.4982 | |
uops_executed_cycles_ge_2_uops_exec | 0.3359 | 0.3787 | 0.3726 | 0.3577 | 0.3575 | 0.3550 | 0.3971 | 0.3922 | 0.3781 | 0.3777 | |
uops_executed_cycles_ge_3_uops_exec | 0.2109 | 0.2338 | 0.2313 | 0.2411 | 0.2416 | 0.1999 | 0.2192 | 0.2159 | 0.2340 | 0.2345 | |
uops_executed_cycles_ge_4_uops_exec | 0.1097 | 0.1216 | 0.1197 | 0.1289 | 0.1294 | 0.0814 | 0.0883 | 0.0871 | 0.1037 | 0.1042 | |
uops_executed_stall_cycles | 0.1445 | 0.2244 | 0.2050 | 0.2624 | 0.1654 | 0.2363 | 0.8175 | 0.6437 | 0.2947 | 0.1826 | |
arith_divider_uops | 0.0086 | 0.0092 | 0.0108 | 0.0007 | 0.0007 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 |
DB12 | DB12np | HS06 | sim | tkreco | ||
---|---|---|---|---|---|---|
cycles | 1.0000 | 1.0000 | 1.0000 | 1.0000 | 1.0000 | |
task-clock | 0.2566 | 0.2578 | 0.3187 | 0.2615 | 0.2572 | |
instructions | 2.6728 | 1.7357 | 1.5060 | 1.3407 | 1.7436 | |
branch-instructions | 0.5319 | 0.2912 | 0.2420 | 0.1767 | 0.2253 | |
branch-misses | 0.0020 | 0.0038 | 0.0061 | 0.0035 | 0.0034 | |
cycle_activity_stalls_mem_any | 0.0417 | 0.1392 | 0.2861 | 0.1846 | 0.1766 | |
cycle_activity_stalls_total | 0.0628 | 0.2256 | 0.3410 | 0.3263 | 0.2222 | |
fp_arith_inst_retired_128b_packed_double | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0585 | |
fp_arith_inst_retired_128b_packed_single | 0.0000 | 0.0000 | 0.0000 | 0.0030 | 0.0128 | |
fp_arith_inst_retired_scalar_double | 0.0247 | 0.1600 | 0.2101 | 0.1789 | 0.1352 | |
fp_arith_inst_retired_scalar_single | 0.0000 | 0.0000 | 0.0003 | 0.0048 | 0.0676 | |
arith_divider_active | 0.0071 | 0.0454 | 0.0077 | 0.1008 | 0.1030 | |
iTLB-load-misses | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | |
iTLB-loads | 0.0000 | 0.0014 | 0.0000 | 0.0011 | 0.0009 | |
icache_16b_ifdata_stall | 0.0111 | 0.0333 | 0.0039 | 0.0447 | 0.0199 | |
mem_load_retired_l1_hit | 0.8858 | 0.3978 | 0.3975 | 0.4051 | 0.4539 | |
mem_load_retired_l2_hit | 0.0050 | 0.0082 | 0.0095 | 0.0095 | 0.0070 | |
mem_load_retired_l3_hit | 0.0000 | 0.0012 | 0.0029 | 0.0025 | 0.0053 | |
mem_load_retired_l3_miss | 0.0000 | 0.0000 | 0.0020 | 0.0003 | 0.0001 | |
offcore_requests_outstanding_demand_data_rd_ge_6 | 0.0000 | 0.0000 | 0.0175 | 0.0015 | 0.0011 | |
resource_stalls_any | 0.0250 | 0.1677 | 0.3411 | 0.3764 | 0.2851 | |
rs_events_empty_cycles | 0.0206 | 0.0752 | 0.0621 | 0.1249 | 0.0415 | |
uops_executed_cycles_ge_1_uop_exec | 0.9375 | 0.7791 | 0.6595 | 0.6744 | 0.7782 | |
uops_executed_cycles_ge_2_uops_exec | 0.8438 | 0.5825 | 0.5359 | 0.5037 | 0.5854 | |
uops_executed_cycles_ge_3_uops_exec | 0.6726 | 0.3864 | 0.3842 | 0.3364 | 0.3823 | |
uops_executed_cycles_ge_4_uops_exec | 0.4412 | 0.2183 | 0.2256 | 0.1811 | 0.2085 | |
uops_executed_stall_cycles | 0.0628 | 0.2248 | 0.3412 | 0.3265 | 0.2223 |
DB12 | DB12np | HS06 | sim | tkreco | ||
---|---|---|---|---|---|---|
instructions | 1.0000 | 1.0000 | 1.0000 | 1.0000 | 1.0000 | |
task-clock | 0.0960 | 0.1485 | 0.2116 | 0.1951 | 0.1475 | |
cycles | 0.3741 | 0.5761 | 0.6640 | 0.7459 | 0.5735 | |
branch-instructions | 0.1990 | 0.1677 | 0.1607 | 0.1318 | 0.1292 | |
branch-misses | 0.0007 | 0.0022 | 0.0040 | 0.0026 | 0.0019 | |
cycle_activity_stalls_mem_any | 0.0156 | 0.0802 | 0.1900 | 0.1377 | 0.1013 | |
cycle_activity_stalls_total | 0.0235 | 0.1300 | 0.2264 | 0.2434 | 0.1274 | |
fp_arith_inst_retired_128b_packed_double | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0336 | |
fp_arith_inst_retired_128b_packed_single | 0.0000 | 0.0000 | 0.0000 | 0.0022 | 0.0073 | |
fp_arith_inst_retired_scalar_double | 0.0093 | 0.0922 | 0.1395 | 0.1335 | 0.0775 | |
fp_arith_inst_retired_scalar_single | 0.0000 | 0.0000 | 0.0002 | 0.0036 | 0.0388 | |
arith_divider_active | 0.0027 | 0.0261 | 0.0051 | 0.0752 | 0.0591 | |
iTLB-load-misses | 0.0000 | 0.0000 | 0.0000 | 0.0000 | 0.0000 | |
iTLB-loads | 0.0000 | 0.0008 | 0.0000 | 0.0008 | 0.0005 | |
icache_16b_ifdata_stall | 0.0042 | 0.0192 | 0.0026 | 0.0333 | 0.0114 | |
mem_load_retired_l1_hit | 0.3314 | 0.2292 | 0.2639 | 0.3021 | 0.2603 | |
mem_load_retired_l2_hit | 0.0019 | 0.0047 | 0.0063 | 0.0071 | 0.0040 | |
mem_load_retired_l3_hit | 0.0000 | 0.0007 | 0.0020 | 0.0019 | 0.0031 | |
mem_load_retired_l3_miss | 0.0000 | 0.0000 | 0.0013 | 0.0002 | 0.0001 | |
offcore_requests_outstanding_demand_data_rd_ge_6 | 0.0000 | 0.0000 | 0.0116 | 0.0011 | 0.0006 | |
resource_stalls_any | 0.0093 | 0.0966 | 0.2265 | 0.2808 | 0.1635 | |
rs_events_empty_cycles | 0.0077 | 0.0433 | 0.0412 | 0.0932 | 0.0238 | |
uops_executed_cycles_ge_1_uop_exec | 0.3508 | 0.4488 | 0.4379 | 0.5030 | 0.4463 | |
uops_executed_cycles_ge_2_uops_exec | 0.3157 | 0.3356 | 0.3558 | 0.3757 | 0.3357 | |
uops_executed_cycles_ge_3_uops_exec | 0.2516 | 0.2226 | 0.2551 | 0.2509 | 0.2193 | |
uops_executed_cycles_ge_4_uops_exec | 0.1651 | 0.1258 | 0.1498 | 0.1351 | 0.1196 | |
uops_executed_stall_cycles | 0.0235 | 0.1295 | 0.2266 | 0.2436 | 0.1275 |