From grillo@scipp.ucsc.edu Tue Jun 20 16:02:54 2000 Date: Mon, 19 Jun 2000 23:21:22 -0700 (PDT) From: Alex Grillo To: "Morrissey, MC (Martin) " Cc: "'Tony Weidberg (LHC) '" , 'Marko Mikuz ' , 'Wladyslaw Dabrowski ' , unno@post.kek.jp, m.morrissey@rl.ac.uk, anghinof@sunvlsi.cern.ch, Ned Spencer Subject: Re: Module connector Hi All, As usual, Martin has provided a very comprehensive description of these connector and connection issues which we have been discussing since at least February. I'd like to add a few extra comments. First, concerning the multiplexing of Temp2 and Reset, this was first proposed as a way to reduce the number of wires in the low mass cable and in the conventional cable between PP2 and PP3. This was because Marko was concerned that there was not enough room to accommodate all the wires in the limited (I think 21mm) width and still allow 2.5mm separation to the high voltage and Michal had determined that the space for this intermediate conventional cable was very tight. Ned and Max developed a circuit model which seemed to work in a breadboard test but without any ABCD. It was proposed that Martin would test this circuit as soon as the harness-1 was available. As Martin has pointed out that has not been tested but will be soon. The problem now is that we are being asked to make a connector decision for Module0 which may be the final one. Also, I'm a little concerned that perhaps we are trying to put too much fancy design into the system when there is clearly a lot to do and not much testing has been done on either the power supply end which must make this muptiplexed signal or on the module end where we are just now starting to look at a spec for the rise time of the Reset signal. The power tape seems able to accommodate the extra line for Temp2 without violating the 2.5mm spacing since it can be put on the BiasRet side of the tape. Also, I think the cable from PP2 to PP3 is turning out to be a little thinner than Michal had estimated so he is not as worried about this extra wire. Therefore, my suggestion now is that we abandon this mupltiplexing idea and keep the Temp1 and Temp2 lines. The second point I want to make is that we need to be careful about our decision not to bring the sense lines onto the hybrid. The current draw is not all that stable in that Icc varies with the DAC settings and Idd varies with occupancy and trigger rate. In fact, there is a large surge on Idd after each trigger which must be supplied by the caps but things may be bouncing around a lot. Also, we should note that we have specified the chip perforance to be valid within a range of +-5% of Vcc and Vdd at the chip pads. Originally, this was mostly given to the power supply people as their margin of regulation. Any voltage drop across the hybrid or variation in drop across connectors eats into the margin allowed for the power supply and distribution system. I'd like to see this analyzed. The other point to make with regard to sense wires is that we are now using DGsense as the sense for the temperature readings. Therefore, any variation in current draw beyond the sense point will increase the error on the temperature reading. Martin makes this point in stating that the Temp refereence should be connected to DGND close to the connector. However, the full variation of DGND currents across the connector must be understood before we remove the DGSense from the connector. I am in favor of keeping the sense wires on the connector and providing the sensing points near the mid-point of the hybrid. regards, Alex