1 Introduction

2 Design Status Update:

• 2015-03-30
• 2015-07-02
• 2015-08-31
• 2015-11-17

3 Hardware

3.1 CaR Board

CaR Board V0.1

CaR board is designed for the operation of 2 FEI4 boards, each FEI4 board can have the following resources:

• Power resource
  • 5 adjustable(0.8 ~ 3.0V), monitored power rails, the maximum current capability is 500 mA;
  • One fixed(can be adjusted by modifying the resistors) monitored 1.8V power rail, the maximum current capability is 1A;
• Bias resource
  • 8 channel adjustable(0.8 ~ 3.0V) bias, output current load capability is ± 20 mA;
• Control signals
  • Input(to FEI4 board)
    • LVCMOS 1.8V × 4
    • LVCMOS 1.5V × 1
  • Output(from FEI4 board)
    • LVCMOS 1.2V × 1
    • LVCMOS 1.5V × 1
• Injection signal
  • One channel, pulse width/height adjustable(0~3.0V)
• LVDS signals
  • 2 pairs of LVDS 2.5V
• Clock
  • 40MHz LVDS 2.5V clock from clock buffer CDCLVD1204
• Analog digitizable channel
  • 3 channels, with sampling rate at 40MHz, signal input range can be adjusted by modifying the gain of the ADC driver

Figure 1. Top side of CaR Board V0.1

Design Files

• Schematic
• Layout
• Gerber File
• BOM

Issues identified

CaR Board V0.2

CaR Board has been revised to V0.2 already but has not been sent out for fabrication yet.

Design Files

• Schematic
• Layout
• Gerber File

3.2 FEI4 board

FEI4 Board V0.1

Design files

• Schematic
• Layout
• Gerber File

FEI4 Board V0.2

Revision list from FEI4 Board V0.1 to V0.2:

1. FEI4 is moved to the higher side;
2. PCIE mini connector is moved to the lower side;
3. RJ45 signal mapping is corrected;
4. All the signal connectors are replaced with LEMO;
5. Board cut out area is enlarged for the convenience of wire bonding;
6. SEAF connectors are replaced with a normal one instead of the original right angle one for lab test;
7. Solder Mask under the FEI4 is removed;

Figure 2. FEI4 board V0.2 with CCPD board V0.2 attached

Design Files

• Schematic
• Layout
• Gerber File
• BOM
• Wire Bonding Block Diagram
• Wire Bonding Guidelines

3.3 CCPD Board

The CCPD board is connected to the FEI4 board through the PCIE mini connector, the CCPD board can have the following resources from FEI4 board:

• Power
  • VCC fixed at 3.3V
  • 3 adjustable(0.8 ~ 3.0V), monitored power rails, the maximum current capability is 500 mA;
• Bias
  • 8 channel adjustable(0.8 ~ 3.0V) bias, output current load capability is ± 20 mA;
• Control signals
  • Input(to FEI4 board)
    • LVCMOS 1.8V × 4
    • LVCMOS 1.5V × 1
  • Output(from FEI4 board)
    • LVCMOS 1.5V × 1
• High Voltage from the LEMO connector on FEI4 board
• Analog digitizable channel
  • 3 channels, with sampling rate at 40MHz, signal input range can be adjusted by modifying the gain of the ADC driver

CCPD Board V0.1

Design Files

• Schematic
• Layout
• Gerber File

Issues identified

1. The offset of PCIe golden finger on the top edge is not correct;
2. Bonding pads are too close to the edge of the cut out of the FEI4 board;

CCPD Board V0.2

Figure 3. Top side of the CCPD board V0.2

Figure 4. Bottom side of the CCPD board V0.2

Design Files

• Schematic
• Layout
• Gerber File
• BOM
• Wire Bonding Guidelines

3.4 VHDCI Adapter Cards

3.4.1 FMC to VHDCI Adapter Card

Figure 5. FMC to VHDCI Adapter Card

Design Files

• Schematic
• Layout
• Gerber File
• BOM

3.4.2 VHDCI to FMC Adapter Card

Figure 6. VHDCI to FMC Adapter Card

Design Files

• Schematic
• Layout
• Gerber File
• BOM

Issues identified

1. The enable of the I2C buffer PCA9614 is controlled by the IO expander PCA9539, the default output of the PCA9539 is '0'. This will make the I2C bus can't work before the PCA9539 is configured properly through I2C bus.
   Currently, we are using a wire connect this net to VCC on the VHDCI2FMC board (Pull up).

4 Firmware

The firmware of CaRIBO u is uploaded to the GitHub repository:

https://github.com/liuhb08/Caribou-FW

5 Software

The software of CaRIBOu system is uploaded to the GitLab repository:

https://gitlab.cern.ch/Caribou/Caribou-SW