EPIC TOF Service Hybrids Project
Project Team and Contacts
The RDO development is a collaboration between BNL, LBNL and Rice University:
Rice: Mike Matveev (
matveev@riceNOSPAMPLEASE.edu), Wei Li (
wl33@riceNOSPAMPLEASE.edu)
BNL: Tonko Ljubicic (
tonko@bnlNOSPAMPLEASE.gov)
JLAB: William Gu (
jgu@jlabNOSPAMPLEASE.org)
Design Requirements and General Notes
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Design Files
Version 1, 13 December 2023
Version 2, 16 January 2024
Version 3, 25 January 2024
Version 4, 1 February 2024
Version 5, 13 February 2024
Version 5a, 23 February 2024 (only one clock pair on the FPGAIO2 page has been modified)
Version 5b, 6 March 2024 (multiple changes in U5 and U7 connections)
Version 5c, 7 March 2024
Version 5d, 12 March 2024
Version 5e, 13 March 2024
Version 5f, 15 March 2024
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Debugging and Modifications, April 2024
Prototype accounting
- Board #1: Rice
- Board #2: Zagreb (Tonko)
- Board #3: Rice
- Board #4: Rice
- Board #5: CEBAF (William)
- Board #6: Rice
Discussion
1.
FPGA_banks.pdf: FPGA banks assignment (Tonko, 3 January 2024)
2.
RDO_clocks.pdf: FPGA clock assignment (William, 3 January 2024)
3.
notes_010424.pdf: Meeting Notes (Tonko, 4 January 2024)
4.
RDOclockPinouts.pdf: Schematic modifications (William, 3 January 2024)
5.
MONITOR.pdf: Current/Voltage measurements (Mike, 3 January 2024)
6.
clocks_011124.pdf: Updated clock diagram (Tonko, 11 January 2024)
7.
FMCV0.pdf: Schematic diagram of the HRPPD FMC board (Tonko, 11 January 2024)
8.
ETROC2_signals.pdf: ETROC2 interface signals (Mike, 11 January 2024)
9.
top.vhd: top.vhd file for the FPGA (Tonko, 15 January 2024)
10.
constraints.xdc constraints.xdc file for the FPGA (Tonko, 15 January 2024)
11.
DC_DC_table.pdf Comparison of bPOL12V, bPOL48V and LTC7890 converters (Tim, 16 January 2024)
12.
William_012224.pdf William's comments on schematic ver.2
13.
Tonko_012324.pdf Tonko's comments on schematic ver.2
14.
tonko_012924.pdf Tonko's comments on schematic ver.3, 01/29/2024
15.
tonko_013024.pdf Tonko's comments on schematic ver.4, 01/30/2024
16.
comments_020624.pdf Tonko's comments on schematic ver.4, 02/06/2024
Interfaces
ETL Module Board (top 3 pictures) and Readout Board v.2. (bottom 2 pictures)
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Optical
FMC Mezzanine
USB
Datasheets, Manuals and User Guides
FPGA Resources
Other Active Parts
Other Passive Parts
Firmware
Presentations
Tonko
This is the
parts list. [external link test]
Downloaded attachment. Artix SBVB484 pin file
here. [local attachment link test]