Super Module Board

DSCN0812.JPG

High Voltage

HT lemo on-board connector 5 6 7 8 4 3 2 1
HV position along the HV-bus 1 2 3 4 5 6 7 8

ADC

Chip

  • The ADC used in the SMB is model AD7998BRUZ-0 (IC19 and IC18 in SMB schematics)
  • The datasheet is this one: 318057847ad7997_8_0.pdf
  • I've checked that after enabling the ADC reading (e->do_adc_read =1;), the clock appears ok
    • period = 12 us (~83 kHz)
    • probe points:
      • HSIO interface-board, connector P2, pin 11 (SCLT_0)
      • SMB board, IC19 / IC18, pin 19 (SCL)

dclock82.jpg

  • after that, the data-line of the ADC starts to ouput data serially. Every 3.2 ms, it seems that there is a polling of the state of the ADC coming from the HSIO ?
dclock84.jpg

  • the protocol seems to be ok, the device answers with the correct address (0x22):
    • the scope screenshot below shows the SCL line (blue channel) and the SDA line (yellow channel). Every logical-bit corresponds in fact to two clock periods (the clock line must be high when interpreting the data-stream).
    • according to the doc concerning the serial interface (page 23 and successive): the master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line SDA, while the serial clock line (SCL) remains high. This indicates that an address/data stream follows. All slave peripherals connected to the serial bus responds to the start condition and shift in the next eight bits, consisting of a7-bit address (MSB first) plus an R/W bit that determines the direction of the data transfer, that is weather data is written to (0) or read (1) from the slave device.
    • after the R/W bit, it is visible that the device enters into tri-state, and the control of the line is taken by the ADC to send its data

lecture_bits.jpg

Sub20 MultiInterface USB adaptor

sub204.jpg

-- SergioGonzalez - 03-Jun-2011

Topic attachments
I Attachment History Action Size Date Who Comment
PDFpdf 318057847ad7997_8_0.pdf r1 manage 1056.6 K 2011-09-09 - 11:33 SergioGonzalez Datasheet ADC7998BRUZ-0
JPEGjpg DSCN0812.JPG r1 manage 1037.4 K 2011-06-03 - 17:31 SergioGonzalez SuperModuleBoard picture
PDFpdf SUB-20-PCB-rev1.1.pdf r1 manage 104.7 K 2011-10-19 - 17:33 SergioGonzalez  
JPEGjpg dclock82.jpg r1 manage 134.1 K 2011-09-09 - 12:14 SergioGonzalez Scope screenshot: ADC@SMB clock line SCL
JPEGjpg dclock83.jpg r1 manage 173.8 K 2011-09-09 - 11:48 SergioGonzalez Scope screenshot: ADC@SMB clock line SCL
JPEGjpg dclock84.jpg r1 manage 157.0 K 2011-09-09 - 11:43 SergioGonzalez Scope screenshot: ADC@SMB SDA data-line (far)
JPEGjpg dclock85.jpg r1 manage 148.7 K 2011-09-09 - 11:43 SergioGonzalez Scope screenshot: ADC@SMB SDA data-line (close)
JPEGjpg dclock86.jpg r1 manage 224.9 K 2011-09-09 - 11:42 SergioGonzalez Scope screenshot: ADC@SMB SDA data-line + clock
PDFpdf dpnc279_sch_v1.pdf r1 manage 200.7 K 2011-06-03 - 17:38 SergioGonzalez SMB v1 schematics
PDFpdf dpnc279_sch_v2.pdf r1 manage 200.6 K 2011-06-17 - 13:08 SergioGonzalez  
JPEGjpg lecture_bits.jpg r1 manage 156.2 K 2011-09-09 - 12:24 SergioGonzalez  
PDFpdf sub20-man.pdf r1 manage 666.4 K 2011-10-19 - 17:35 SergioGonzalez  
JPEGjpg sub204.jpg r1 manage 39.5 K 2011-10-19 - 17:44 SergioGonzalez  
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Topic revision: r6 - 2016-08-26 - SergioGonzalez
 
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