Table of Contents

Thesises

• Diploma thesis: CERN-THESIS-2011-383
• PhD thesis: CERN-THESIS-2016-085

Software

Printed Circuit Boards

Adapter Cards

Generic

FMC to VHDCI Rev. B

• Description:
  • Connects all 34 LVDS pairs of the VHDCI connector to the FMC.
  • No buffering to conserve flexibility concerning IO standard and direction. (Not yet tested).

FMC to VHDCI

• Schematic: pdf
• Layout: pdf
• Eagle design files: zip
• BOM: xlsx

FE-I4

Quad FE-I4 Rev. A

• Description:
  • Connects 4 FE-I4 style RJ45 connectors to the FMC connector.
  • LVDS signals are buffered and fixed in direction
• Errata:
  • RJ45 connector mounted on wrong side of PCB, only 2.5V CMOS averrable for TTL signals.

FMC to Quad FE-I4 adapter card loaded

• Schematic: pdf
• Layout: pdf
• Eagle design files: zip

Quad FE-I4 Rev. B

• Description:
  • Connected 4 FE-I4 style RJ45 connectors to the FMC connector.
  • LVDS signals are buffered.
• Errata:
  • ADC I2C not connected to FMC, Lemo connectors level shifting uni-directional.

FMC to Quad FE-I4 adapter card loaded

• Schematic: pdf
• Layout: pdf
• Eagle design files: zip

VHDCI to 8xRJ45 FE-I4 Rev. A

• Description:
  • Connected 8 FE-I4 style RJ45 connectors to the VHDCI connector.
  • LVDS signals are buffered.
  • 3 GPIOs (direction via solder jumpers)
• Errata:
  • Draws to much current for micro USB
  • GPIO circuit needs mod

VHDCI to 8xFE-I4 adapter card loaded

• Schematic: pdf
• Gerbers: zip
• BOM: xlsx

FE65-P2 Cards

Single Chip Card Rev. A

• Description: PCB carrier for a single FE65-P2 chip. Only passives located on the board itself. Solder jumpers connect CMOS signals to edge connector.

FE65-P2 SCC loaded top side	FE65-P2 SCC loaded bottom side
FE65-P2 SCC unloaded top side	FE65-P2 SCC unloaded bottom side

• Schematic: pdf
• Layout: pdf
• Eagle design files: zip
• Bond diagram: top pads, bottom pads
• Guide: slides

Single Chip Card Rev. B

• Schematic: pdf
• Layout: pdf
• Eagle design files: zip
• Changes:
  • HV filter C/R in right order

Adapter Card Rev. B

• Description:
  • PCB to drive FE65-P2 SCC. Receives LVDS signals which get converted to the necessary 1.2V CMOS level.
  • Powered via micro USB. On board reference current and pulser circuit (to be tested).
  • To be used with FMC to VHDCI board, but can also provide signals via test header (see picture of initial testing)
• Errata:
  • Pulser DAC does not have accessible test pins, only connected to VHDCI.
  • LDOs need additional bypass capacitance.
  • 1.2V LED does not light up (needs higher voltage)
• Notes for Rev C:
  • Add connector to supply 1.2V/3.3V from PS instead of LDO.
  • Add connector to supply 5V from PS instead of micro USB.
  • Add two Lemos to VHDCI, one output & one input. (E.g. busy out, trigger in)

FE65-P2 adapter card loaded and connected (VHDCI bypassed for initial testing)

FE65-P2 adapter card unloaded PCB

• Schematic: pdf
• Layout: pdf
• Eagle design files: zip
• Guide: slides

Adapter Card Rev. C

• Schematic: pdf
• Layout: pdf
• Changes:
  • Added 2 GPIOs (Lemo connector) with level shifter, direction set by solder jumper
  • Added Molex connector for 5V supply
  • Added additional bypass caps to LDOs
  • 1.2V LED switched by transistor and powered from 3.3V
  • Added 5V power LED indicator
  • Fixed IRef current circuit and added extra R for trimming
  • Connected CSb of DAC to VHDCI
  • Added OpAmp to Pulser output, should enable full DAC range from 0 - 1.2V
  • Added RJ45 directly connected to VHDCI, can be used for FE-I4 or EuDet TLU
• Errata:
  • OpAmp does not work properly, it needs a negative rail to proper fall time
  • ...

Adapter Card Rev. D

• Schematic: pdf
• Layout: pdf
• Eagle design files: zip
• Changes:
  • Added -5V converter for OpAmp
  • ...
• Errata:
  • OpAmp rings

AMAC Test boards

AMAC SCC Rev. A

• Description:
  • PCB to hold one AMACv1 chip and route all connections out to pin headers.
  • All outer pins are GND, inner pins are labeled
• Schematic: pdf
• Layout: pdf
• Eagle design files: zip

AMAC SCC Rev. B

• Description:
  • PCB to hold one AMACv1*A* chip and route all connections out to pin headers.
  • All outer pins are GND, inner pins are labeled
• Schematic: pdf
• Layout: pdf
• Eagle design files: zip

AMAC Test Card Rev. A

• Description:
  • Mezzanine board supposed to be plugged into a Mojov3 board
  • Connecteds to AMAC SCC via two 34pin ribbon cable
  • Needs +5V/-5V symmetric power supply, supplied via Molex 4 pin connector
• Schematic: pdf
• Layout: pdf
• Eagle design files: zip

Powerboard

Powerboard v2

• • Powerboard v2 for ITk Strip module
• Errata:
  • J7 stop mask not removed
  • PGOOD from Feast can't be registered in AMAC

Powerboard v2

• Schematic: pdf
• Gerbers revA: zip
• Gerbers revB: zip

PBv2 Test Adapter

• • Test board to mount a PBv2 on top
• Errata:
  • VIN/VIN_RTN swapped
  • VOUT/VOUT_RTN swapped

PBv2 test adapter

• Schematic: pdf
• Layout: pdf
• Design files (KICAD): github